Step 3: Creating Timing Constraints - 2021.1 English

Vivado Design Suite Tutorial: Using Constraints (UG945)

Document ID
UG945
Release Date
2021-08-13
Version
2021.1 English

In this step, you will open the synthesized design and use the Vivado® Timing Constraints wizard. The Timing Constraints wizard analyzes the gate level netlist and finds missing constraints. Use the Timing Constraints wizard to generate constraints for this design.

  1. From the Flow Navigator, click Open Synthesized Design.
  2. When the synthesized design opens, click Constraints Wizard under the Synthesized Design section.

    The introduction page of the Timing Constraints wizard appears. This page describes the types of constraints that the wizard creates: Clocks, Input and Output Ports, and Clock Domain Crossings.

  3. After reading the page, click Next to continue.

    The Primary Clocks page of the Timing Constraints wizard displays all the clock sources with a missing clock definition. For this design, the wizard detected five missing clock constraints that are needed to time logical paths, and four missing clock constraints that are only needed to verify pulse width and minimum or maximum period requirements.



    You will fill in the periods for the five missing primary clocks in the design. The second category of clocks, shown in the Constraints for Pulse Width Check Only table, is optional. For this example, do not add these last constraints.

  4. In the Recommended Constraints table, each row of the wizard is a missing constraint. To specify a constraint in the table, click the cell in the period column for the clock and type the value from the following table to fill in the periods of the five missing primary clocks in the design. When you set the period for a clock, the frequency is automatically populated.
    Table 1. Values to Use on the Primary Clock Page of the Wizard
    Primary Clock Period (ns)
    mgtEngine/ROCKETIO_WRAPPER_i/gt0_ROCKETIO_WRAPPER_TILE_i/GT0_TXOUTCLK_OUT 12.8
    mgtEngine/ROCKETIO_WRAPPER_i/gt0_ROCKETIO_WRAPPER_TILE_i/GT2_TXOUTCLK_OUT 12.8
    mgtEngine/ROCKETIO_WRAPPER_i/gt0_ROCKETIO_WRAPPER_TILE_i/GT4_TXOUTCLK_OUT 12.8
    mgtEngine/ROCKETIO_WRAPPER_i/gt0_ROCKETIO_WRAPPER_TILE_i/GT6_TXOUTCLK_OUT 12.8
    sysClk 10.0

    If you do not want to enter a constraint for a specific clock, uncheck the box next to the clock.

    For more information about how the wizard finds these missing constraints, click the Quick Help button (“?”) in the lower left-hand corner of the wizard. The quick help pages are context specific and contain more information about the topologies the wizard is looking for and an explanation as to why the constraint is being suggested.

    The completed page looks like the following figure.



  5. Click Next to continue.

    The primary clock constraints have been added to the design. Next, the wizard looks for unconstrained generated clocks. Generated clocks are derived from primary clocks in the FPGA fabric. A good example would be a binary counter used to create a divided clock.

    In this design, the wizard determined that there are no unconstrained generated clocks.

  6. Click Next to continue.

    Next, the wizard looks for forwarded clocks. A forwarded clock is a generated clock on a primary output port of the FPGA. These are commonly used for source synchronous buses when the capture clock travels with the data.

    The wizard has determined that there are no unconstrained forwarded clocks in the design.
  7. Click Next to continue.

    Next, the wizard looks for external feedback delays. MMCM or PLL feedback delay outside the FPGA is used to compute the clock delay compensation in the timing reports.

    The wizard did not find any unconstrained MMCM external feedback delays in the design.

  8. Click Next to continue.

    Next, the wizard looks at the input delays. The following figure shows the Input Delay page of the Timing Constraints wizard. There are three sections to the page.



    In section A, you can see all the input ports that are missing input delay constraints in the design. In this table, you select the timing template you would like to use to constrain the input.

    In section B, you provide the delay values for the template. This section will change depending on the template chosen in section A.

    In section C, there are three tabs:

    Tcl Command Preview
    Previews the Tcl commands that will be used to constrain the design.
    Existing Set Input Delay Constraints
    Shows input delay constraints that exist in the design.
    Waveform
    Displays the waveform associated with the template.

    Next, you will fill out the form based on the following table.

  9. Click the Clock column header to sort the table alphabetically by clock name.
  10. Select the template in section A, enter the values in section B, and observe the Tcl commands, existing input delays, and the template specific waveform in section C.
  11. Skip entering the first four constraints shown in following table by unchecking the box to the left of the constraint. In this particular case, you false path these paths from the GTPRESET_IN port later, as it is an asynchronous reset signal synchronized inside the design.

    The blocks of colored rows in the following table can all be entered at the same time in the Input Delays page of the Timing Constraints wizard, shown in the following figure, by selecting multiple rows in the wizard (use the Shift or Ctrl buttons and click to select multiple rows) and then entering the values once. Some inputs are constrained relative to virtual clocks, because they are captured by an internal generated clock with a waveform different than the board clock. In this case, the wizard creates a virtual clock with the same frequency and waveform as the internal clock, and recommends a constraint relative to the virtual clock.

    The following table is shaded to indicate which groups of signals can be entered in this manner.

    Table 2. Input Constrain Values
    Interface Clock Synchronous Alignment Data Rate and Edge tco_min (ns) tco_max (ns) trce_dly_min (ns) trce_dly_max (ns)
    GTPRESET_IN mgtEngine/... System Edge Single Rise Uncheck constraint – will false path later
    GTPRESET_IN mgtEngine/... System Edge Single Rise Uncheck constraint – will false path later
    GTPRESET_IN mgtEngine/... System Edge Single Rise Uncheck constraint – will false path later
    GTPRESET_IN mgtEngine/... System Edge Single Rise Uncheck constraint – will false path later
    DataIn_pad_0_i[*] sysClk System Edge Single Rise 1 2 1 1
    DataIn_pad_1_i[*] sysClk System Edge Single Rise 1 2 1 1
    LineState_pad_0_i[*] sysClk System Edge Single Rise 1 2 1 1
    LineState_pad_1_i[*] sysClk System Edge Single Rise 1 2 1 1
    VStatus_pad_0_i[*] sysClk System Edge Single Rise 1 2 1 1
    VStatus_pad_1_i[*] sysClk System Edge Single Rise 1 2 1 1
    RxActive_pad_0_i sysClk System Edge Single Rise 1 2 1 1
    RxActive_pad_1_i sysClk System Edge Single Rise 1 2 1 1
    Rx_Error_pad_0_i sysClk System Edge Single Rise 1 2 1 1
    Rx_Error_pad_1_i sysClk System Edge Single Rise 1 2 1 1
    Rx_Valid_pad_0_i sysClk System Edge Single Rise 1 2 1 1
    Rx_Valid_pad_1_i sysClk System Edge Single Rise 1 2 1 1
    TxReady_pad_0_i sysClk System Edge Single Rise 1 2 1 1
    TxReady_pad_1_i sysClk System Edge Single Rise 1 2 1 1
    usb_vbus_paf_0_i sysClk System Edge Single Rise 1 2 1 1
    usb_vbus_paf_1_i sysClk System Edge Single Rise 1 2 1 1
    or1200_clmode VIRTUAL_cpuClk_5 System Edge Single Rise 0.1 2.5 0.1 0.2
    or1200_pic_ints VIRTUAL_cpuClk_5 System Edge Single Rise 0.1 2.5 0.1 0.2
    reset VIRTUAL_cpuCLK_5 System Edge Single Rise 0.1 2.5 0.1 0.2

    The following figure shows the completed input delay page. Note the four constraints being skipped.



  12. When you have successfully entered all the input constraint values, click Next.

    The Output Delays page of the wizard displays all the outputs that are unconstrained in the design. The page layout is very similar to the inputs page.

  13. In the Output Delays page, click the Clock header to sort the table alphabetically by clock name.
  14. Use the following table to constrain all the outputs as you did for the input constraint values. You can select multiple lines in the wizard at once and edit several entries as the same time.
    Table 3. Output Constraint Values
    Interface Clock Synchronous Alignment Data Rate and Edge tsu (ns) thd (ns) trce_dly_max (ns) trce_dly_min (ns)
    OpMode_pad_0_o[*] sysClk System Setup/Hold Single Rise 1.0 0.1 0.1 0.1
    OpMode_pad_1_o[*] sysClk System Setup/Hold Single Rise 1.0 0.1 0.1 0.1
    VControl_pad_0_o[*] sysClk System Setup/Hold Single Rise 1.0 0.1 0.1 0.1
    VControl_pad_0_o[*] sysClk System Setup/Hold Single Rise 1.0 0.1 0.1 0.1
    SuspendM_pad_0_o sysClk System Setup/Hold Single Rise 1.0 0.1 0.1 0.1
    SuspendM_pad_1_o sysClk System Setup/Hold Single Rise 1.0 0.1 0.1 0.1
    TermSel_pad_0_o sysClk System Setup/Hold Single Rise 1.0 0.1 0.1 0.1
    TermSel_pad_1_o sysClk System Setup/Hold Single Rise 1.0 0.1 0.1 0.1
    TxValid_pad_0_o sysClk System Setup/Hold Single Rise 1.0 0.1 0.1 0.1
    TxValid_pad_1_o sysClk System Setup/Hold Single Rise 1.0 0.1 0.1 0.1
    VControl_Load_pad_0_o sysClk System Setup/Hold Single Rise 1.0 0.1 0.1 0.1
    VControl_Load_pad_1_o sysClk System Setup/Hold Single Rise 1.0 0.1 0.1 0.1
    XcvSelect_pad_0_o sysClk System Setup/Hold Single Rise 1.0 0.1 0.1 0.1
    XcvSelect_pad_1_o sysClk System Setup/Hold Single Rise 1.0 0.1 0.1 0.1
    phy_rst_pad_0_o sysClk System Setup/Hold Single Rise 1.0 0.1 0.1 0.1
    phy_rst_pad_1_o sysClk System Setup/Hold Single Rise 1.0 0.1 0.1 0.1
    DataOut_pad_0_o[*] VIRTUAL_wbClk_4 System Setup/Hold Single Rise 2.1 0.6 0.1 0.0
    DataOut_pad_1_o[*] VIRTUAL_wbClk_4 System Setup/Hold Single Rise 2.1 0.6 0.1 0.0
    or1200_pm_out[*] VIRTUAL_wbClk_4 System Setup/Hold Single Rise 2.1 0.6 0.1 0.0
  15. Click Next to continue.

    The wizard looks for any unconstrained combinational paths through the design. A combinational path is a path that traverses the FPGA without being captured by any sequential elements. This design does not contain any combinational paths.

  16. Click Next to continue.

    Physically exclusive clock groups are clocks that do not exist in the design at the same time. There are no unconstrained physically exclusive clock groups in this design.

  17. Click Next to continue.

    Logically exclusive clocks with no interaction are clocks that are active at the same time except on shared clock tree sections. Then these clocks do not have logical paths between each other and outside the shared sections, they are logically exclusive. There are no unconstrained logically exclusive clock groups with no interaction in the design.

  18. Click Next to continue.

    Logically exclusive clocks with interaction are clocks that are active at the same time except on shared clock tree sections. When these clocks have logical paths between each other, only the clocks limited to the shared clock tree sections are logically exclusive and are therefore constrained differently than the logically exclusive clock with no interaction. There are no unconstrained logically exclusive clock groups with interaction in the design.

  19. Click Next to continue.

    The Asynchronous Clock Domain Crossings page recommends constraints for safe clock domain crossings. This design does not contain any unconstrained clock domain crossings.

  20. Click Next to continue.

    The following figure shows the final page of the Timing Constraints wizard. All the constraints that were generated by the wizard can be viewed by clicking the links. If you would like to run any reports once the wizard is finished, you can select them using the check boxes in the wizard.



  21. Click Finish to complete the Timing Constraints wizard.