Step 7: Timing Summary Report - 2021.1 English

Vivado Design Suite Tutorial: Using Constraints (UG945)

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2021.1 English

Timing paths start and end at clocked elements. Input and Output ports are not sequential elements, and by default Vivado timing analysis does not time paths to or from I/O ports in the design, unless input/output delay constraints are specified.

In this step you will generate and interpret timing reports in Vivado.

  1. Select Reports > Timing > Report Timing Summary.
  2. Click OK to generate the report, using the default options.

    The Timing Summary tab opens, as shown in the following figure.

    The design passes setup timing but fails hold analysis. Before implementing the design, timing analysis uses estimated net delays that represent ideal placement. Small hold violations are common at this point of the flow and will be fixed during the routing step. For now, review the content of the report.

  3. Click the Worst Negative Slack link in the design timing summary section to see the worst timing path in the design, as shown in the following figure.

  4. When the worst path is selected, press the F4 key to bring up its schematic. The following figure shows the worst setup path in the design.

  5. In the timing summary tree, select Check Timing.
    • There are nine issues flagged by Check Timing shown in the following figure.
    • Eight of these are pulse_width_clock checks, which were also flagged by the Timing Constraints wizard, but were not constrained. These violations have low severity because the corresponding missing clocks are not needed for timing logic paths.
    • The remaining issue flagged by Check Timing is a no_input_delay check, which is due to a missing input constraint on the reset signal that was set to false_path. This can also be ignored in this example.

  6. In the timing summary tree, select the Clock Summary, as shown in the following figure.

    The clock summary section of the timing summary report lists all the clocks in the design and shows the resulting frequencies and waveforms of each clock. The hierarchy shows the relationship between the generated clocks and the primary clock (for example, cpuClk_5 vs. sysClk). For example, it shows that cpuClk_5 is generated from primary clock SysClk, and its period is twice that of sysClk.

    The remaining sections of the timing summary report group paths by their type. Each section lists the top ten paths (specified when the report was generated) in that group. These include inter-clock paths, intra-clock paths, other path groups, user ignored paths, and unconstrained paths. Clicking the roots will show a summary of the paths beneath. Expanding the tree further will ultimately display the top timing paths for each group.