DFX Controller IP for 7 Series Devices - 2021.1 English

Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947)

Document ID: UG947
Release Date: 2021-12-17
Version: 2021.1 English

Introduction
Navigating Content by Design Process
Hardware and Software Requirements
Tutorial Design Description
7 Series Basic DFX Flow
Step 1: Extract the Tutorial Design Files
Step 2: Examining the Scripts
Step 3: Synthesizing the Design
Step 4: Assembling and Implementing the Design
Step 5: Building the Design Floorplan
Step 6: Implementing the First Configuration
Step 7: Implementing the Second Configuration
Step 8: Examining the Results with Highlighting Scripts
Step 9: Generating Bitstreams
Step 10: Partially Reconfiguring the FPGA
Conclusion
UltraScale and UltraScale+ Basic DFX Flow
Step 1: Extract the Tutorial Design Files
Step 2: Examining the Scripts
Step 3: Synthesizing the Design
Step 4: Assembling and Implementing the Design
Step 5: Build the Design Floorplan
Step 6: Implementing the First Configuration
Step 7: Implementing the Second Configuration
Step 8: Examine the Results with Highlighting Scripts
Step 9: Generating the Bitstreams
Step 10: Partially Reconfiguring the FPGA
Conclusion
DFX RTL Project Flow
Step 1: Extract the Tutorial Design Files
Step 2: Load Initial Design Sources
Step 3: Completing the Design with the Dynamic Function eXchange Wizard
Step 4: Synthesizing and Implementing the Current Design
Step 5: Adding an Additional Reconfigurable Model and Corresponding Configuration
Step 6: Creating and Implementing a Greybox Module
Step 7: Modifying a Design Source or Options
Conclusion
Vivado Debug and the DFX Project Flow
Step 1: Extract the Tutorial Design Files
Step 2: Loading Initial Design Sources
Step 3: Setting Up the Design for DFX
Step 4: Using the DFX Wizard to Complete the Rest of the Design
Step 5: Adding IP in the Reconfigurable Module
Step 6: Synthesizing the Design and Creating a Floorplan
Step 7: Running the PR Configuration Analysis Report
Step 8: Implementing the Design
Step 9: Adding an Additional Reconfigurable Module and Corresponding Configuration
Step 10: Generating Bitstreams
Step 11: Connecting to the Board and Programming the FPGA
Conclusion
DFX Controller IP for 7 Series Devices
Step 1: Extract the Tutorial Design Files
Step 2: Customizing the Dynamic Function eXchange (DFX) Controller IP
Step 3: Compiling the Design
Step 4: Setting up the Board
Step 5: Operating the Sample Design
Step 6: Querying the DFX Controller in the FPGA
Step 7: Modifying the DFX Controller in the FPGA
Conclusion
DFX Controller for UltraScale Devices
Step 1: Extract the Tutorial Design Files
Step 2: Customizing the Dynamic Function eXchange (DFX) Controller IP
Step 3: Compiling the Design
Step 4: Setting up the Board
Step 5: Operating the Sample Design
Step 6: Querying the DFX Controller in the FPGA
Step 7: Modifying the DFX Controller in the FPGA
Conclusion
DFX Controller IP for UltraScale+ Devices
Step 1: Extract the Tutorial Design Files
Step 2: Processing the Tutorial Design
Step 3: Running the Tutorial Design
Program the QSPI Flash Device
Manage Reconfiguration via Software
Monitor Dynamic Function eXchange via Debug Cores
Insert CRC Failures and View the FPGA Response
Conclusion
Nested Dynamic Function eXchange
Overview
Step 1: Extracting the Tutorial Design Files
Step 2: Examining the Scripts
The Synthesis Scripts
The Nested DFX Scripts
Step 3: Synthesizing the Design
Step 4: Assembling and Implementing the Design
Implementation Design Flow
Static Design Updates
Verification Passes
Bitstream Creation
Step 5: Test the Design in Hardware
Configuring the Device with a Full Image
Partially Reconfiguring the Device
Load partial bitstreams for UltraScale+ devices
Load partial bitstreams for UltraScale devices
Conclusion
Abstract Shell for Dynamic Function eXchange
Overview
Step 1: Extracting the Tutorial Design Files
Step 2: Processing the Tutorial Design
Step 3: Create Abstract Shells
Step 4: Implement New RM within Abstract Shells
Step 5: Validate the Design in Hardware
Approach 1: Generate Partial Bitstreams from Full Configurations
Approach 2: Generate Partial Bitstreams from Abstract Shells
Complete Hardware Validation
Conclusion
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
Additional Resources
Revision History
Please Read: Important Legal Notices

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