In order to test this tutorial design in hardware, a few additional steps are required. These steps include:
- Building the Vitis application project to run in MicroBlaze
- Creating the full design bitstream with this application present
- Generating all partial bitstreams and the PROM image
- Loading the PROM image in hardware and running hardware tests
Because this design is the same one used for the DFX Controller tutorial in Lab 7, the same process is used to generate the software application and operate the design in hardware. Rather than reiterate these details here, the following steps will reference the appropriate steps in Lab 7. However, given that the Abstract Shell solution was used to generate some of the partial bitstreams, the bitstream generation scripts have been modified.
- If the main project_dfxc_vcu118 project has been closed, reopen it within Vivado.
- Turn to Lab 7, Step 2, Instruction 8 and follow this lab through Instruction
23.
Bitstream generation can be done in two ways when using Abstract Shell. The first is the standard way, where a full design is open in Vivado and both full and partial bitstreams are generated. Alternatively, partial bitstreams only can be generated directly from the Abstract Shell implementation for any RM.
The following two sections describe the Vivado Tcl commands used to create partial bitstreams using each of these methodologies. The set of commands are embedded in the Tcl script noted at the beginning of each section. Choose one approach and call the script for that approach before moving on to hardware validation.