IP Versions and Revision Control - 2021.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2021-08-18
Version
2021.1 English

When IP is customized, the tool creates an XCI file containing all the selected parameterization values. Each Vivado IDE version supports only one version of an IP. Xilinx recommends that you use this latest IP version. If you use an older IP version, you must save all the output products for the older version. For information about source management and revision control, see this link in the Vivado Design Suite User Guide: Design Flows Overview (UG892).

Important: For memory IP in 7 series devices, a PRJ file is created in addition to the XCI file. When using revision control with 7 series memory IP, keep the PRJ file in the same directory as the XCI file.