Reduce the Number of Partition Pins - 2021.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2021-08-18
Version
2021.1 English

In a DFX design, signals between the reconfigurable module (RM) and static region are called boundary signals. All RM pins must have a partition pin location constraint (PPLOC) deposited on the boundary signal by the placer. The only exceptions are dedicated paths between hard primitives. The partition pin is the physical interface on fabric that separates the static and reconfigurable portions of a boundary signal. For more information on PPLOCs, see this link in the Vivado Design Suite User Guide: Dynamic Function eXchange (UG909).

The presence of partition pins reduces the solution space for the router, because the related boundary net is always forced to route through the partition pin. To alleviate this issue, the DFX flow includes expanded routing. Expanded routing is the additional routing footprint for a reconfigurable partition (RP) that can include routing tiles from the static region. For more information on expanded routing, see this link in the Vivado Design Suite User Guide: Dynamic Function eXchange (UG909).

The boundary nets of an RM have fanout in the static region as well as within the RM. In a DFX design, the loads of boundary net in the static region are called static Endpoints. When the static Endpoint of a boundary net is placed in the expanded routing footprint of an RP, PPLOC reduction occurs in the router for that boundary signal. This allows the router to reroute the boundary net from a static Endpoint to an RM Endpoint during subsequent RM implementations, instead of locking boundary nets down to a PPLOC. Xilinx recommends expanded routing to reduce the dependency of the router on PPLOCs.

In the following example, the routing footprint of the reconfigurable Pblock (pblock_dynamic_region) is the same as the reconfigurable Pblock size (CLOCKREGION_X0Y4: CLOCKREGION_X4Y10). All of the static region logic is assigned to the static Pblock region (pblock_static_region), which is outside the routing footprint of the reconfigurable Pblock. Therefore, PPLOC reduction is not triggered, and the reconfigurable Pblock contains a large number of PPLOCs after route_design.

Figure 1. Static Endpoints Outside Expanded Routing Footprint of RP

In the following example, the static Endpoints to the reconfigurable Pblock (pblock_dynamic_region) are assigned to a thin static Pblock (pblock_ii_blp_ulp_pipe_0), which is defined in the expanded routing footprint of the RP Pblock. There are no PPLOCs remaining after route_design.

Figure 2. Static Endpoints to the RP Pblock Assigned to the Static Pblock

To achieve maximum PPLOC reduction, Xilinx recommends that you guide the placer to keep static Endpoints in the expanded routing footprint of the reconfigurable Pblock. One way to achieve this is to use thin static Pblocks defined in the expanded routing footprint of the reconfigurable Pblock.

Tip: To highlight the tiles in the routing footprint of a reconfigurable Pblock, source the <pblock_name>_Routing_AllTiles.tcl Tcl script generated by the placer and located in the hd_visual folder in the implementation directory.