Replicate Static Register Driving Multiple RPs - 2021.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2021-08-18
Version
2021.1 English

To ensure that a static Endpoint is not shared by multiple reconfigurable partitions (RPs), avoid single registers that drive multiple RPs. The DFX-1 DRC flags this violation.

In the following example, a single static register drives multiple RPs as well as static logic. This approach is not recommended in the DFX flow.

Figure 1. One Static Register Driving Multiple RPs and Static Logic

In the following example, two separate but equivalent registers drive two RPs. This is the recommended approach when using the DFX flow.

Figure 2. Two Registers Driving Two RPs