Reviewing Timing Constraints - 2021.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2021-08-18
Version
2021.1 English

You must provide clean timing constraints, along with timing exceptions, where applicable. Bad constraints result in long compile time, performance issues, and hardware failures.