Worst Case Power Analysis Using Xilinx Power Estimator (XPE) - 2021.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2021-08-18
Version
2021.1 English

Xilinx recommends designing the board for worst-case power. For details, see this link in the Vivado Design Suite User Guide: Power Analysis and Optimization (UG907).