IDELAYE2 - 2021.1 English

Vivado Design Suite 7 Series FPGA and Zynq-7000 SoC Libraries Guide (UG953)

Document ID
UG953
Release Date
2021-06-16
Version
2021.1 English

Primitive: Input Fixed or Variable Delay Element

Introduction

Every I/O block contains a programmable absolute delay element called IDELAYE2. The IDELAYE2 can be connected to an input register/ISERDESE2 or driven directly into FPGA logic. The IDELAYE2 is a 31-tap, wraparound, delay element with a calibrated tap resolution. Refer to the 7 series FPGA Data Sheet for delay values. The IDELAYE2 allows incoming signals to be delayed on an individual basis. The tap delay resolution is varied by selecting an IDELAYCTRL reference clock from the range specified in the 7 series FPGA Data Sheet.

Port Descriptions

Port Direction Width Function
C Input 1 All control inputs to IDELAYE2 primitive (RST, CE, and INC) are synchronous to the clock input (C). A clock must be connected to this port when IDELAYE2 is configured in "VARIABLE", "VAR_LOAD" or "VAR_LOAD_PIPE" mode. C can be locally inverted, and must be supplied by a global or regional clock buffer. This clock should be connected to the same clock in the SelectIO logic resources (when using ISERDESE2 and OSERDESE2, C is connected to CLKDIV).
CE Input 1 Active-High enable for increment/decrement function.
CINVCTRL Input 1 The CINVCTRL pin is used for dynamically switching the polarity of C pin. This is for use in applications when glitches are not an issue. When switching the polarity, do not use the IDELAYE2 control pins for two clock cycles.
CNTVALUEIN <4:0> Input 5 Counter value from FPGA logic for dynamically loadable tap value input.
CNTVALUEOUT <4:0> Output 5 The CNTVALUEOUT pins are used for reporting the dynamically switching value of the delay element. CNTVALUEOUT is only available when IDELAYE2 is in "VAR_LOAD" or "VAR_LOAD_PIPE" mode.
DATAIN Input 1 The DATAIN input is directly driven by the FPGA logic providing a logic accessible delay line. The data is driven back into the FPGA logic through the DATAOUT port with a delay set by the IDELAY_VALUE. DATAIN can be locally inverted. The data cannot be driven to an I/O.
DATAOUT Output 1 Delayed data from either the IDATAIN or DATAIN input paths. DATAOUT connects to an ISERDESE2, input register or FPGA logic.
IDATAIN Input 1 The IDATAIN input is driven by its associated I/O. The data can be driven to either an ISERDESE2 or input register block, directly into the FPGA logic, or to both through the DATAOUT port with a delay set by the IDELAY_VALUE.
INC Input 1 Selects whether tap delay numbers will be incremented or decremented. INC = 1 increments when CE is high. INC=0 decrements.
LD Input 1
  • In “VARIABLE” mode, loads the value set by the IDELAY_VALUE attribute. The default value is zero.
  • In “VAR_LOAD” mode, loads the value of CNTVALUEIN. The value present at CNTVALUEIN[4:0] will be the new tap value.
  • In “VAR_LOAD_PIPE” mode, loads the value currently in the pipeline register. The value present in the pipeline register will be the new tap value.
LDPIPEEN Input 1 When High, loads the pipeline register with the value currently on the CNTVALUEIN pins.
REGRST Input 1 When high, resets the pipeline register to all zeros. Only used in "VAR_LOAD_PIPE" mode.

Design Entry Method

Instantiation Yes
Inference No
IP Catalog Yes
Macro support No

Available Attributes

Attribute Type Allowed Values Default Description
CINVCTRL_SEL STRING "FALSE", "TRUE" "FALSE" Enables the CINVCTRL_SEL pin to dynamically switch the polarity of the C pin.
DELAY_SRC STRING "IDATAIN", "DATAIN" "IDATAIN" Select the delay source input to the IDELAYE2.
  • "IDATAIN": IDELAYE2 chain input is IDATAIN.
  • "DATAIN": IDELAYE2 chain input is DATAIN.
HIGH _PERFORMANCE _MODE STRING "FALSE", "TRUE" "FALSE" When TRUE, this attribute reduces the output jitter. When FALSE, power consumption is reduced. The difference in power consumption is quantified in the Xilinx Power Estimator tool.
IDELAY_TYPE STRING "FIXED", "VARIABLE", "VAR_LOAD", "VAR_LOAD_PIPE" "FIXED" Sets the type of tap delay line.
  • "FIXED": Sets a static delay value.
  • "VARIABLE": Dynamically adjust (increment/decrement) delay value.
  • "VAR_LOAD": Dynamically loads tap values.
  • "VAR_LOAD_PIPE": Pipelined dynamically loadable tap values.
IDELAY_VALUE DECIMAL 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 0 Specifies the fixed number of delay taps in fixed mode or the initial starting number of taps in "VARIABLE" mode (input path). When IDELAY_TYPE is set to "VAR_LOAD" or "VAR_LOAD_PIPE" mode, this value is ignored.
PIPE_SEL STRING "FALSE", "TRUE" "FALSE" Select pipelined mode.
REFCLK _FREQUENCY 1 significant digit FLOAT 190-210, 290-310 MHz 200.0 Sets the tap value (in MHz) used by the timing analyzer for static timing analysis and functional/timing simulation. The frequency of REFCLK must be within the given datasheet range to guarantee the tap-delay value and performance.
SIGNAL_PATTERN STRING "DATA", "CLOCK" "DATA" Causes the timing analyzer to account for the appropriate amount of delay-chain jitter in the data or clock path.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- IDELAYE2: Input Fixed or Variable Delay Element
--           7 Series
-- Xilinx HDL Language Template, version 2021.1

IDELAYE2_inst : IDELAYE2
generic map (
   CINVCTRL_SEL => "FALSE",          -- Enable dynamic clock inversion (FALSE, TRUE)
   DELAY_SRC => "IDATAIN",           -- Delay input (IDATAIN, DATAIN)
   HIGH_PERFORMANCE_MODE => "FALSE", -- Reduced jitter ("TRUE"), Reduced power ("FALSE")
   IDELAY_TYPE => "FIXED",           -- FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
   IDELAY_VALUE => 0,                -- Input delay tap setting (0-31)
   PIPE_SEL => "FALSE",              -- Select pipelined mode, FALSE, TRUE
   REFCLK_FREQUENCY => 200.0,        -- IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
   SIGNAL_PATTERN => "DATA"          -- DATA, CLOCK input signal
)
port map (
   CNTVALUEOUT => CNTVALUEOUT, -- 5-bit output: Counter value output
   DATAOUT => DATAOUT,         -- 1-bit output: Delayed data output
   C => C,                     -- 1-bit input: Clock input
   CE => CE,                   -- 1-bit input: Active high enable increment/decrement input
   CINVCTRL => CINVCTRL,       -- 1-bit input: Dynamic clock inversion input
   CNTVALUEIN => CNTVALUEIN,   -- 5-bit input: Counter value input
   DATAIN => DATAIN,           -- 1-bit input: Internal delay data input
   IDATAIN => IDATAIN,         -- 1-bit input: Data input from the I/O
   INC => INC,                 -- 1-bit input: Increment / Decrement tap delay input
   LD => LD,                   -- 1-bit input: Load IDELAY_VALUE input
   LDPIPEEN => LDPIPEEN,       -- 1-bit input: Enable PIPELINE register to load data input
   REGRST => REGRST            -- 1-bit input: Active-high reset tap-delay input
);

-- End of IDELAYE2_inst instantiation

Verilog Instantiation Template


// IDELAYE2: Input Fixed or Variable Delay Element
//           7 Series
// Xilinx HDL Language Template, version 2021.1

(* IODELAY_GROUP = <iodelay_group_name> *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL

IDELAYE2 #(
   .CINVCTRL_SEL("FALSE"),          // Enable dynamic clock inversion (FALSE, TRUE)
   .DELAY_SRC("IDATAIN"),           // Delay input (IDATAIN, DATAIN)
   .HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
   .IDELAY_TYPE("FIXED"),           // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
   .IDELAY_VALUE(0),                // Input delay tap setting (0-31)
   .PIPE_SEL("FALSE"),              // Select pipelined mode, FALSE, TRUE
   .REFCLK_FREQUENCY(200.0),        // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
   .SIGNAL_PATTERN("DATA")          // DATA, CLOCK input signal
)
IDELAYE2_inst (
   .CNTVALUEOUT(CNTVALUEOUT), // 5-bit output: Counter value output
   .DATAOUT(DATAOUT),         // 1-bit output: Delayed data output
   .C(C),                     // 1-bit input: Clock input
   .CE(CE),                   // 1-bit input: Active high enable increment/decrement input
   .CINVCTRL(CINVCTRL),       // 1-bit input: Dynamic clock inversion input
   .CNTVALUEIN(CNTVALUEIN),   // 5-bit input: Counter value input
   .DATAIN(DATAIN),           // 1-bit input: Internal delay data input
   .IDATAIN(IDATAIN),         // 1-bit input: Data input from the I/O
   .INC(INC),                 // 1-bit input: Increment / Decrement tap delay input
   .LD(LD),                   // 1-bit input: Load IDELAY_VALUE input
   .LDPIPEEN(LDPIPEEN),       // 1-bit input: Enable PIPELINE register to load data input
   .REGRST(REGRST)            // 1-bit input: Active-high reset tap-delay input
);

// End of IDELAYE2_inst instantiation

Related Information

  • See the 7 Series FPGA SelectIO Resources User Guide (UG471).