PULLDOWN - 2021.1 English

Vivado Design Suite 7 Series FPGA and Zynq-7000 SoC Libraries Guide (UG953)

Document ID
UG953
Release Date
2021-06-16
Version
2021.1 English

Primitive: Resistor to GND for Input Pads, Open-Drain, and 3-State Outputs

Introduction

This resistor element is connected to input, output, or bidirectional pads to guarantee a logic Low level for nodes that might float.

Port Descriptions

Port Direction Width Function
O Output 1 Pulldown output (connect directly to top level port)

Design Entry Method

Instantiation Yes
Inference No
IP Catalog No
Macro support No

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- PULLDOWN: I/O Buffer Weak Pull-down
--           7 Series
-- Xilinx HDL Language Template, version 2021.1

PULLDOWN_inst : PULLDOWN
port map (
   O => O     -- Pulldown output (connect directly to top-level port)
);

-- End of PULLDOWN_inst instantiation

Verilog Instantiation Template


// PULLDOWN: I/O Buffer Weak Pull-down
//           7 Series
// Xilinx HDL Language Template, version 2021.1

PULLDOWN PULLDOWN_inst (
   .O(O)     // Pulldown output (connect directly to top-level port)
);

// End of PULLDOWN_inst instantiation

Related Information

  • See the 7 Series FPGA SelectIO Resources User Guide (UG471).