RAMB36E2 - 2021.1 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2021-06-16
Version
2021.1 English

Primitive: 36K-bit Configurable Synchronous Block RAM

  • PRIMITIVE_GROUP: BLOCKRAM
  • PRIMITIVE_SUBGROUP: BRAM
  • Families: UltraScale, UltraScale+

Introduction

The RAMB36E2 allows access to the block RAM memory in the 36 Kb configuration. This element can be configured and used as a 1-bit wide by 32K deep to an 36-bit wide by 1024-bit deep true dual port RAM. This element can also be configured as a 72-bit wide by 512 deep simple dual port RAM. Both read and write operations are fully synchronous to the supplied clock(s) to the component. However, the READ and WRITE ports can operate fully independent and asynchronous to each other, accessing the same memory array. When configured in the wider data width modes, byte-enable write operations are possible, and an optional output register can be used to reduce the clock-to-out times of the RAM. This RAM also features a cascade capability, which lets you chain multiple RAMB36E2 components to form deeper and more power efficient memory configurations if desired.

Port Descriptions

Port Direction Width Function
Cascade Signals: Signals used when cascading more than one RAMB36E2 components
CASDIMUXA Input 1 Port A mux control input to select between normal data input (DINA) when Low or CASCADE data input (CASDINA) when High.
CASDIMUXB Input 1 Port B mux control input to select between normal data input (DINB) when Low or CASCADE data input (CASDINB) when High.
CASDINA<31:0> Input 32 Port A cascade input data.
CASDINB<31:0> Input 32 Port B cascade input data.
CASDINPA<3:0> Input 4 Port A cascade input parity data.
CASDINPB<3:0> Input 4 Port B cascade input parity data.
CASDOMUXA Input 1 Port A mux control input to select between output data from BRAM (registered or unregistered) or CASCADE data input (CASDINA).
CASDOMUXB Input 1 Port B mux control input to select between output data from BRAM (registered or unregistered) or CASCADE data input (CASDINB).
CASDOMUXEN_A Input 1 Port A unregistered output data register enable.
CASDOMUXEN_B Input 1 Port B unregistered output data register enable.
CASDOUTA<31:0> Output 32 Port A cascade output data.
CASDOUTB<31:0> Output 32 Port B cascade output data.
CASDOUTPA<3:0> Output 4 Port A cascade output parity data.
CASDOUTPB<3:0> Output 4 Port B cascade output parity data.
CASINDBITERR Input 1 Cascaded double-bit error (DBITERR) signal from prior block RAM in the cascade chain.
CASINSBITERR Input 1 Cascaded single bit error (SBITERR) signal from prior block RAM in the cascade chain.
CASOREGIMUXA Input 1 Port A mux control input to select between output data from BRAM or CASCADE data input (CASDINA).
CASOREGIMUXB Input 1 Port B mux control input to select between output data from BRAM or CASCADE data input (CASDINB).
CASOREGIMUXEN_A Input 1 Port A registered output data register enable.
CASOREGIMUXEN_B Input 1 Port B registered output data register enable.
CASOUTDBITERR Output 1 Cascaded double-bit error (DBITERR) signal to next block RAM in the cascade chain.
CASOUTSBITERR Output 1 Cascaded single bit error (SBITERR) signal to next block RAM in the cascade chain.
ECC Signals: Error Correction Circuitry ports
DBITERR Output 1 Status output from ECC function to indicate a double bit error was detected during a read operation. EN_ECC_READ needs to be TRUE to use this functionality. Synchronous to RDCLK.
ECCPARITY<7:0> Output 8 8-bit data generated by the ECC encoder used by the ECC decoder for memory error detection and correction. Applicable when EN_ECC_WRITE=1. Synchronous to WRCLK.
ECCPIPECE Input 1 Clock enable for the ECC pipeline register.
INJECTDBITERR Input 1 Applicable when EN_ECC_WRITE=1. Causes a double-bit error to be inserted on bits 30 and 62 of DI during a write operation. Synchronous to WRCLK.
INJECTSBITERR Input 1 Applicable when EN_ECC_WRITE=1. Causes a single-bit error to be inserted on bit 30 of DI during a write operation.
RDADDRECC<8:0> Output 9 Read address for ECC function.
SBITERR Output 1 ECC output indicating that a single-bit error was detected during the read operation. Synchronous to RDCLK.
Port A Address/Control Signals: Port A address and control (clock, reset, enables, etc.) signals.
ADDRARDADDR<14:0> Input 15 Port A address input bus/Read address input bus.
ADDRENA Input 1 Active-High port A address input bus/Read address input bus.
CLKARDCLK Input 1 Port A clock input/Read clock input.
ENARDEN Input 1 Port A RAM enable/Read enable. For best power characteristics of this component, it is suggested to drive this pin Low when ever a new read or write operation is not necessary on Port A. Significant power savings can be seen when this port is driven Low.
REGCEAREGCE Input 1 Port A output register clock enable input/Output register clock enable input (valid only when DOA_REG=1).
RSTRAMARSTRAM Input 1 Synchronous data latch set/reset to value indicated by SRVAL_A. RSTRAMARSTRAM sets/resets the BRAM data output latch when DO_REG=0 or 1. If DO_REG=1 there is a cycle of latency between the internal data latch node that is reset by RSTRAMARSTRAM and the DO output of the BRAM. This signal resets port A RAM output when READ_WIDTH≤36 and the entire RAM output when READ_WIDTH=72.
RSTREGARSTREG Input 1 Synchronous output register set/reset to value indicated by SRVAL_A. RSTREGARSTREG sets/resets the output register when DO_REG=1. RSTREG_PRIORITY_A determines if this signal gets priority over REGCEAREGCE. This signal resets port A output when READ_WIDTH≤36 and the entire RAM output when READ_WIDTH=72.
SLEEP Input 1 Dynamic shut down power saving. If SLEEP is High, the block is in power saving mode. If SLEEP_ASYNC=FALSE, synchronous to RDCLK, otherwise, asynchronous input. Using this pin can save additional power if the RAM is not accessed for sustained amounts of time.
WEA<3:0> Input 4 Port A byte-wide write enable. In the case that port A is write-only and byte-write operation is not necessary, it is suggested to connect all bits high and control write operation with the ENARDEN port. Doing this improves power consumption of the block RAM. In wide 72-bit mode or if port A is read-only or not used, tie all bits Low. In other modes, the connections are dependent on WRITE_WIDTH_A setting. See the UltraScale Architecture Memory Resources User Guide (UG573) for WEA mapping for different port widths.
Port A Data: Port A data signals.
DINADIN<31:0> Input 32 Port A data input bus. When WRITE_WIDTH=72, DINADIN is the logical DI<31:0>.
DINPADINP<3:0> Input 4 Port A parity data input bus/Data parity input bus addressed by WRADDR. When WRITE_WIDTH=72, DINPADINP is the logical DIP<3:0>.
DOUTADOUT<31:0> Output 32 Port A data output bus. When READ_WIDTH=72, DOUTADOUT is the logical DO<31:0>.
DOUTPADOUTP<3:0> Output 4 Port A parity data output bus. When READ_WIDTH=72, DOUTPADOUT is the logical DOP<3:0>.
Port B Address/Control Signals: Port B address and control (clock, reset, enables, etc.).
ADDRBWRADDR<14:0> Input 15 Port B address input bus/Write address input bus.
ADDRENB Input 1 Active-High port B address input bus/Write address input bus.
CLKBWRCLK Input 1 Port B clock input/Write clock input.
ENBWREN Input 1 Port B RAM enable/Write enable. For best power characteristics of this component, it is suggested to drive this pin Low when ever a new read or write operation is not necessary on Port B. Significant power savings can be seen when this port is driven Low.
REGCEB Input 1 Port B output register clock enable (valid only when DOB_REG=1 and READ_WIDTH≤36).
RSTRAMB Input 1 Synchronous data latch set/reset to value indicated by SRVAL_B. RSTRAMB sets/resets the BRAM data output latch when DO_REG=0 or 1. If DO_REG=1 there is a cycle of latency between the internal data latch node that is reset by RSTRAMB and the DO output of the BRAM. Not used when READ_WIDTH=72.
RSTREGB Input 1 Synchronous output register set/reset to value indicated by SRVAL_B. RSTREGB sets/resets the output register when DO_REG=1. RSTREG_PRIORITY_B determines if this signal gets priority over REGCEB. Not used when READ_WIDTH=72.
WEBWE<7:0> Input 8 Port B byte-wide write enable/Write enable. In the case that port B is write-only and byte-write operation is not necessary, it is suggested to connect all bits high and control write operation with the ENBWREN port. Doing this improves power consumption of the block RAM. When using ECC mode, all bits must be tied high. In the case that port B is read-only or not used, tie all bits Low. In other modes, the connections are dependent on WRITE_WIDTH_B setting. See the UltraScale Architecture Memory Resources User Guide (UG573) for WEBWE mapping for different port widths.
Port B Data: Port B data signals.
DINBDIN<31:0> Input 32 Port B data input bus. When WRITE_WIDTH=72, DINBDIN is the logical DI<63:32>.
DINPBDINP<3:0> Input 4 Port B parity data input bus/Data parity input bus addressed by WRADDR. When WRITE_WIDTH=72, DINPBDINP is the logical DIP<7:4>.
DOUTBDOUT<31:0> Output 32 Port B data output bus. When READ_WIDTH=72, DOUTBDOUT is the logical DO<63:32>.
DOUTPBDOUTP<3:0> Output 4 Port B parity data output bus. When READ_WIDTH=72, DOUTPBDOUTP is the logical DOP<7:4>.

Design Entry Method

Instantiation Yes
Inference Recommended
IP and IP Integrator Catalog Yes

Available Attributes

Attribute Type Allowed Values Default Description
CASCADE_ORDER_A, CASCADE_ORDER_B: Specifies the order of the cascaded BRAM. FIRST BRAM is the bottom in cascade, LAST one is on the top of the cascade, and MIDDLE is the BRAM in between bottom and top.
CASCADE_ORDER_A STRING "NONE", "FIRST", "LAST", "MIDDLE" "NONE" Specifies the cascade order for Port A.
CASCADE_ORDER_B STRING "NONE", "FIRST", "LAST", "MIDDLE" "NONE" Specifies the cascade order for Port B.
CLOCK_DOMAINS: Used for Simulation purposes to model the address collision case as well as to enable lower power operation in common clock mode.
  • "COMMON": Common Clock/Single Clock.
  • "INDEPENDENT": Independent Clock/Dual Clock.
CLOCK_DOMAINS STRING "INDEPENDENT", "COMMON" "INDEPENDENT" Used for Simulation purposes to model the address collision case as well as to enable lower power operation in common clock mode.
  • "COMMON": Common Clock/Single Clock.
  • "INDEPENDENT": Independent Clock/Dual Clock.
Collision check: Modifies the simulation behavior if a memory collision occurs.
  • "ALL": Warning produced and affected outputs/memory go unknown (X).
  • "WARNING_ONLY": Warning produced and affected outputs/memory retain last value.
  • "GENERATE_X_ONLY": No warning and affected outputs/memory go unknown (X).
  • "NONE": No warning and affected outputs/memory retain last value.
Note: Use this setting carefully. Setting it to a value other than "ALL" can mask design problems during simulation.
SIM_COLLISION_CHECK STRING "ALL", "GENERATE_X_ONLY", "NONE", "WARNING_ONLY" "ALL" Modifies the simulation behavior if a memory collision occurs.
  • "ALL": Warning produced and affected outputs/memory go unknown (X).
  • "WARNING_ONLY": Warning produced and affected outputs/memory retain last value.
  • "GENERATE_X_ONLY": No warning and affected outputs/memory go unknown (X).
  • "NONE": No warning and affected outputs/memory retain last value.
Note: Use this setting carefully. Setting it to a value other than "ALL" can mask design problems during simulation.
DOA_REG, DOB_REG: A value of 1 enables the output registers to the RAM enabling higher performance clock-to-out from the RAM at the expense of an added clock cycle of read latency. A value of 0 allows a read in one clock cycle but will result in slower clock-to-out timing.
DOA_REG DECIMAL 1, 0 1 A value of 1 enables the output registers to the RAM enabling higher performance clock-to-out from the RAM at the expense of an added clock cycle of read latency. A value of 0 allows a read in one clock cycle but will result in slower clock-to-out timing.
DOB_REG DECIMAL 1, 0 1 A value of 1 enables the output registers to the RAM enabling higher performance clock-to-out from the RAM at the expense of an added clock cycle of read latency. A value of 0 allows a read in one clock cycle but will result in slower clock-to-out timing.
ENADDRENA/ENADDRENB: Specifies if Address Enable pin is enabled.
ENADDRENA STRING "FALSE", "TRUE" "FALSE" Specifies if Address Enable pin is enabled.
ENADDRENB STRING "FALSE", "TRUE" "FALSE" Specifies if Address Enable pin is enabled.
EN_ECC_PIPE: Enable ECC pipeline output register stage.
EN_ECC_PIPE STRING "FALSE", "TRUE" "FALSE" Enable ECC pipeline output register stage.
EN_ECC_READ: Enable the ECC read decoder circuitry. Only valid when READ_WIDTH is set to 72.
EN_ECC_READ STRING "FALSE", "TRUE" "FALSE" Enable the ECC read decoder circuitry. Only valid when READ_WIDTH is set to 72.
EN_ECC_WRITE: Enable the ECC write encoder circuitry. When using ECC mode, byte-write capability is not supported, and the WEBWE signals must all be tied high to ensure proper operation. Only valid when WRITE_WIDTH is set to 72.
EN_ECC_WRITE STRING "FALSE", "TRUE" "FALSE" Enable the ECC write encoder circuitry. When using ECC mode, byte-write capability is not supported, and the WEBWE signals must all be tied high to ensure proper operation. Only valid when WRITE_WIDTH is set to 72.
INIT_A, INIT_B: Specifies the initial value on the port output after configuration.
INIT_A HEX Any 36-bit HEX value All zeroes Specifies the initial value on the port output after configuration.
INIT_B HEX Any 36-bit HEX value All zeroes Specifies the initial value on the port output after configuration.
INIT_00 to INIT_7F: Specifies the initial contents of the 32 Kb data memory array.
INIT_00 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_0A HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_0B HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_0C HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_0D HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_0E HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_0F HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_01 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_1A HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_1B HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_1C HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_1D HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_1E HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_1F HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_02 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_2A HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_2B HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_2C HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_2D HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_2E HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_2F HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_03 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_3A HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_3B HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_3C HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_3D HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_3E HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_3F HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_04 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_4A HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_4B HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_4C HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_4D HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_4E HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_4F HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_05 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_5A HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_5B HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_5C HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_5D HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_5E HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_5F HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_06 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_6A HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_6B HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_6C HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_6D HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_6E HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_6F HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_07 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_7A HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_7B HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_7C HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_7D HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_7E HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_7F HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_08 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_09 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_10 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_11 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_12 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_13 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_14 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_15 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_16 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_17 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_18 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_19 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_20 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_21 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_22 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_23 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_24 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_25 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_26 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_27 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_28 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_29 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_30 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_31 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_32 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_33 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_34 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_35 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_36 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_37 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_38 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_39 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_40 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_41 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_42 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_43 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_44 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_45 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_46 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_47 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_48 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_49 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_50 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_51 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_52 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_53 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_54 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_55 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_56 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_57 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_58 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_59 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_60 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_61 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_62 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_63 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_64 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_65 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_66 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_67 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_68 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_69 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_70 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_71 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_72 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_73 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_74 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_75 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_76 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_77 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_78 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
INIT_79 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 32 Kb data memory array.
Initialization File: File name of file used to specify initial RAM contents.
INIT_FILE STRING String "NONE" File name of file used to specify initial RAM contents.
INITP_00 to INITP_0F: Specifies the initial contents of the 4 Kb parity data memory array.
INITP_00 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 4 Kb parity data memory array.
INITP_0A HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 4 Kb parity data memory array.
INITP_0B HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 4 Kb parity data memory array.
INITP_0C HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 4 Kb parity data memory array.
INITP_0D HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 4 Kb parity data memory array.
INITP_0E HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 4 Kb parity data memory array.
INITP_0F HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 4 Kb parity data memory array.
INITP_01 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 4 Kb parity data memory array.
INITP_02 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 4 Kb parity data memory array.
INITP_03 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 4 Kb parity data memory array.
INITP_04 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 4 Kb parity data memory array.
INITP_05 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 4 Kb parity data memory array.
INITP_06 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 4 Kb parity data memory array.
INITP_07 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 4 Kb parity data memory array.
INITP_08 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 4 Kb parity data memory array.
INITP_09 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 4 Kb parity data memory array.
Programmable Inversion Attributes: Specifies whether or not to use the optional inversions on specific pins of this component to change the active polarity of the pin function. When set to 1 on a clock pin (WRCLK or RDCLK), this components clocks on the negative edge. When set to 1 on other pins, it changes the function to behave active-Low rather than active-High. For pins that are buses, the bit-width of this attribute should match that of the bit-width of the associated pins and a binary value indicates which inverters to use and which to bypass. If an external inverter is specified on one of these associated pins, the Vivado Design Suite will automatically set this attribute during the opt_design stage so that additional logic is not necessary for changing the input polarity.
IS_CLKARDCLK_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the CLKARDCLK pin.
IS_CLKBWRCLK_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the CLKBWRCLK pin.
IS_ENARDEN_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the ENARDEN pin.
IS_ENBWREN_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the ENBWREN pin.
IS_RSTRAMARSTRAM_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the RSTRAMARSTRAM pin.
IS_RSTRAMB_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the RSTRAMB pin.
IS_RSTREGARSTREG_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the RSTREGARSTREG pin.
IS_RSTREGB_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the RSTREGB pin.
RDADDRCHANGE: Read Address Change is a feature which will prevent memory access when the output value does not change thus saving power. Setting this attribute to TRUE enables this power-saving feature. Setting it to FALSE improves setup time to the RAM possibly improving block RAM performance. This feature is limited to uninitialized block RAM in the UltraScale Architecture. This feature is available to all block RAM in the UltraScale+ Architecture.
RDADDRCHANGEA STRING "FALSE", "TRUE" "FALSE" Specifies whether or not to use the Read Address Change feature for port A.
RDADDRCHANGEB STRING "FALSE", "TRUE" "FALSE" Specifies whether or not to use the Read Address Change feature for port B.
READ_WIDTH_A/B, WRITE_WIDTH_A/B: Specifies the desired data width for a read/write on port A/B, including parity bits. This value must be 0 if the port is not used. Otherwise, it should be set to the desired port width.
READ_WIDTH_A DECIMAL 0, 1, 2, 4, 9, 18, 36, 72 0 Specifies the desired data width for a read/write on port A/B, including parity bits. This value must be 0 if the port is not used. Otherwise, it should be set to the desired port width.
READ_WIDTH_B DECIMAL 0, 1, 2, 4, 9, 18, 36 0 Specifies the desired data width for a read/write on port A/B, including parity bits. This value must be 0 if the port is not used. Otherwise, it should be set to the desired port width.
WRITE_WIDTH_A DECIMAL 0, 1, 2, 4, 9, 18, 36 0 Specifies the desired data width for a read/write on port A/B, including parity bits. This value must be 0 if the port is not used. Otherwise, it should be set to the desired port width.
WRITE_WIDTH_B DECIMAL 0, 1, 2, 4, 9, 18, 36, 72 0 Specifies the desired data width for a read/write on port A/B, including parity bits. This value must be 0 if the port is not used. Otherwise, it should be set to the desired port width.
RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Selects register priority for RSTREG or REGCE.
RSTREG_PRIORITY_A STRING "RSTREG", "REGCE" "RSTREG" Selects register priority for RSTREG or REGCE.
RSTREG_PRIORITY_B STRING "RSTREG", "REGCE" "RSTREG" Selects register priority for RSTREG or REGCE.
Sleep Async: Specifies whether the SLEEP pin is synchronous to the CLKARDCLK pin ("FALSE") or treated as an asynchronous pin.
SLEEP_ASYNC STRING "FALSE", "TRUE" "FALSE" Specifies whether the SLEEP pin is synchronous to the CLKARDCLK pin ("FALSE") or treated as an asynchronous pin.
SRVAL_A, SRVAL_B: Specifies the output value of the RAM upon assertion of the synchronous reset (RST/RSTREG) signal.
SRVAL_A HEX Any 36-bit HEX value All zeroes Specifies the output value of the RAM upon assertion of the synchronous reset (RST/RSTREG) signal.
SRVAL_B HEX Any 36-bit HEX value All zeroes Specifies the output value of the RAM upon assertion of the synchronous reset (RST/RSTREG) signal.
WriteMode: Specifies output behavior of the port being written to.
  • "WRITE_FIRST": Written value appears on output port of the RAM.
  • "READ_FIRST": Previous RAM contents for that memory location appear on the output port. When the same clock is used for both ports, this mode also allows address collision avoidance when reading and writing to the same address from different ports.
  • "NO_CHANGE": Previous value on the output port remains the same. This is the lowest power mode.
When using the RAM as a simple dual-port (one port is read-only and one is write-only) it is suggested to set the WRITE_MODEs to NO_CHANGE if using different clocks on both ports or if address collisions can be avoided. It is suggested to set this to READ_FIRST mode only if using the same clock on both ports and address collisions can not be avoided in the design. WRITE_FIRST mode is not suggested to be used for simple dual-port operation as it consumes additional power over NO_CHANGE mode with no functional difference.
WRITE_MODE_A STRING "NO_CHANGE", "READ_FIRST", "WRITE_FIRST" "NO_CHANGE" Specifies output behavior of the port being written to.
  • "WRITE_FIRST": Written value appears on output port of the RAM.
  • "READ_FIRST": Previous RAM contents for that memory location appear on the output port. When the same clock is used for both ports, this mode also allows address collision avoidance when reading and writing to the same address from different ports.
  • "NO_CHANGE": Previous value on the output port remains the same. This is the lowest power mode.
When using the RAM as a simple dual-port (one port is read-only and one is write-only) it is suggested to set the WRITE_MODEs to NO_CHANGE if using different clocks on both ports or if address collisions can be avoided. It is suggested to set this to READ_FIRST mode only if using the same clock on both ports and address collisions can not be avoided in the design. WRITE_FIRST mode is not suggested to be used for simple dual-port operation as it consumes additional power over NO_CHANGE mode with no functional difference.
WRITE_MODE_B STRING "NO_CHANGE", "READ_FIRST", "WRITE_FIRST" "NO_CHANGE" Specifies output behavior of the port being written to.
  • "WRITE_FIRST": Written value appears on output port of the RAM.
  • "READ_FIRST": Previous RAM contents for that memory location appear on the output port. When the same clock is used for both ports, this mode also allows address collision avoidance when reading and writing to the same address from different ports.
  • "NO_CHANGE": Previous value on the output port remains the same. This is the lowest power mode.
When using the RAM as a simple dual-port (one port is read-only and one is write-only) it is suggested to set the WRITE_MODEs to NO_CHANGE if using different clocks on both ports or if address collisions can be avoided. It is suggested to set this to READ_FIRST mode only if using the same clock on both ports and address collisions can not be avoided in the design. WRITE_FIRST mode is not suggested to be used for simple dual-port operation as it consumes additional power over NO_CHANGE mode with no functional difference.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- RAMB36E2: 36K-bit Configurable Synchronous Block RAM
--           UltraScale
-- Xilinx HDL Language Template, version 2021.1

RAMB36E2_inst : RAMB36E2
generic map (
   -- CASCADE_ORDER_A, CASCADE_ORDER_B: "FIRST", "MIDDLE", "LAST", "NONE"
   CASCADE_ORDER_A => "NONE",
   CASCADE_ORDER_B => "NONE",
   -- CLOCK_DOMAINS: "COMMON", "INDEPENDENT"
   CLOCK_DOMAINS => "INDEPENDENT",
   -- Collision check: "ALL", "GENERATE_X_ONLY", "NONE", "WARNING_ONLY"
   SIM_COLLISION_CHECK => "ALL",
   -- DOA_REG, DOB_REG: Optional output register (0, 1)
   DOA_REG => 1,
   DOB_REG => 1,
   -- ENADDRENA/ENADDRENB: Address enable pin enable, "TRUE", "FALSE"
   ENADDRENA => "FALSE",
   ENADDRENB => "FALSE",
   -- EN_ECC_PIPE: ECC pipeline register, "TRUE"/"FALSE"
   EN_ECC_PIPE => "FALSE",
   -- EN_ECC_READ: Enable ECC decoder, "TRUE"/"FALSE"
   EN_ECC_READ => "FALSE",
   -- EN_ECC_WRITE: Enable ECC encoder, "TRUE"/"FALSE"
   EN_ECC_WRITE => "FALSE",
   -- INITP_00 to INITP_0F: Initial contents of parity memory array
   INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
   INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
   INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
   INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
   INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
   INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
   -- INIT_00 to INIT_7F: Initial contents of data memory array
   INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
   -- INIT_A, INIT_B: Initial values on output ports
   INIT_A => X"000000000",
   INIT_B => X"000000000",
   -- Initialization File: RAM initialization file
   INIT_FILE => "NONE",
   -- Programmable Inversion Attributes: Specifies the use of the built-in programmable inversion
   IS_CLKARDCLK_INVERTED => '0',
   IS_CLKBWRCLK_INVERTED => '0',
   IS_ENARDEN_INVERTED => '0',
   IS_ENBWREN_INVERTED => '0',
   IS_RSTRAMARSTRAM_INVERTED => '0',
   IS_RSTRAMB_INVERTED => '0',
   IS_RSTREGARSTREG_INVERTED => '0',
   IS_RSTREGB_INVERTED => '0',
   -- RDADDRCHANGE: Disable memory access when output value does not change ("TRUE", "FALSE")
   RDADDRCHANGEA => "FALSE",
   RDADDRCHANGEB => "FALSE",
   -- READ_WIDTH_A/B, WRITE_WIDTH_A/B: Read/write width per port
   READ_WIDTH_A => 0,                                                               -- 0-9
   READ_WIDTH_B => 0,                                                               -- 0-9
   WRITE_WIDTH_A => 0,                                                              -- 0-9
   WRITE_WIDTH_B => 0,                                                              -- 0-9
   -- RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG", "REGCE")
   RSTREG_PRIORITY_A => "RSTREG",
   RSTREG_PRIORITY_B => "RSTREG",
   -- SRVAL_A, SRVAL_B: Set/reset value for output
   SRVAL_A => X"000000000",
   SRVAL_B => X"000000000",
   -- Sleep Async: Sleep function asynchronous or synchronous ("TRUE", "FALSE")
   SLEEP_ASYNC => "FALSE",
   -- WriteMode: "WRITE_FIRST", "NO_CHANGE", "READ_FIRST"
   WRITE_MODE_A => "NO_CHANGE",
   WRITE_MODE_B => "NO_CHANGE"
)
port map (
   -- Cascade Signals outputs: Multi-BRAM cascade signals
   CASDOUTA => CASDOUTA,               -- 32-bit output: Port A cascade output data
   CASDOUTB => CASDOUTB,               -- 32-bit output: Port B cascade output data
   CASDOUTPA => CASDOUTPA,             -- 4-bit output: Port A cascade output parity data
   CASDOUTPB => CASDOUTPB,             -- 4-bit output: Port B cascade output parity data
   CASOUTDBITERR => CASOUTDBITERR,     -- 1-bit output: DBITERR cascade output
   CASOUTSBITERR => CASOUTSBITERR,     -- 1-bit output: SBITERR cascade output
   -- ECC Signals outputs: Error Correction Circuitry ports
   DBITERR => DBITERR,                 -- 1-bit output: Double bit error status
   ECCPARITY => ECCPARITY,             -- 8-bit output: Generated error correction parity
   RDADDRECC => RDADDRECC,             -- 9-bit output: ECC Read Address
   SBITERR => SBITERR,                 -- 1-bit output: Single bit error status
   -- Port A Data outputs: Port A data
   DOUTADOUT => DOUTADOUT,             -- 32-bit output: Port A Data/LSB data
   DOUTPADOUTP => DOUTPADOUTP,         -- 4-bit output: Port A parity/LSB parity
   -- Port B Data outputs: Port B data
   DOUTBDOUT => DOUTBDOUT,             -- 32-bit output: Port B data/MSB data
   DOUTPBDOUTP => DOUTPBDOUTP,         -- 4-bit output: Port B parity/MSB parity
   -- Cascade Signals inputs: Multi-BRAM cascade signals
   CASDIMUXA => CASDIMUXA,             -- 1-bit input: Port A input data (0=DINA, 1=CASDINA)
   CASDIMUXB => CASDIMUXB,             -- 1-bit input: Port B input data (0=DINB, 1=CASDINB)
   CASDINA => CASDINA,                 -- 32-bit input: Port A cascade input data
   CASDINB => CASDINB,                 -- 32-bit input: Port B cascade input data
   CASDINPA => CASDINPA,               -- 4-bit input: Port A cascade input parity data
   CASDINPB => CASDINPB,               -- 4-bit input: Port B cascade input parity data
   CASDOMUXA => CASDOMUXA,             -- 1-bit input: Port A unregistered data (0=BRAM data, 1=CASDINA)
   CASDOMUXB => CASDOMUXB,             -- 1-bit input: Port B unregistered data (0=BRAM data, 1=CASDINB)
   CASDOMUXEN_A => CASDOMUXEN_A,       -- 1-bit input: Port A unregistered output data enable
   CASDOMUXEN_B => CASDOMUXEN_B,       -- 1-bit input: Port B unregistered output data enable
   CASINDBITERR => CASINDBITERR,       -- 1-bit input: DBITERR cascade input
   CASINSBITERR => CASINSBITERR,       -- 1-bit input: SBITERR cascade input
   CASOREGIMUXA => CASOREGIMUXA,       -- 1-bit input: Port A registered data (0=BRAM data, 1=CASDINA)
   CASOREGIMUXB => CASOREGIMUXB,       -- 1-bit input: Port B registered data (0=BRAM data, 1=CASDINB)
   CASOREGIMUXEN_A => CASOREGIMUXEN_A, -- 1-bit input: Port A registered output data enable
   CASOREGIMUXEN_B => CASOREGIMUXEN_B, -- 1-bit input: Port B registered output data enable
   -- ECC Signals inputs: Error Correction Circuitry ports
   ECCPIPECE => ECCPIPECE,             -- 1-bit input: ECC Pipeline Register Enable
   INJECTDBITERR => INJECTDBITERR,     -- 1-bit input: Inject a double-bit error
   INJECTSBITERR => INJECTSBITERR,
   -- Port A Address/Control Signals inputs: Port A address and control signals
   ADDRARDADDR => ADDRARDADDR,         -- 15-bit input: A/Read port address
   ADDRENA => ADDRENA,                 -- 1-bit input: Active-High A/Read port address enable
   CLKARDCLK => CLKARDCLK,             -- 1-bit input: A/Read port clock
   ENARDEN => ENARDEN,                 -- 1-bit input: Port A enable/Read enable
   REGCEAREGCE => REGCEAREGCE,         -- 1-bit input: Port A register enable/Register enable
   RSTRAMARSTRAM => RSTRAMARSTRAM,     -- 1-bit input: Port A set/reset
   RSTREGARSTREG => RSTREGARSTREG,     -- 1-bit input: Port A register set/reset
   SLEEP => SLEEP,                     -- 1-bit input: Sleep Mode
   WEA => WEA,                         -- 4-bit input: Port A write enable
   -- Port A Data inputs: Port A data
   DINADIN => DINADIN,                 -- 32-bit input: Port A data/LSB data
   DINPADINP => DINPADINP,             -- 4-bit input: Port A parity/LSB parity
   -- Port B Address/Control Signals inputs: Port B address and control signals
   ADDRBWRADDR => ADDRBWRADDR,         -- 15-bit input: B/Write port address
   ADDRENB => ADDRENB,                 -- 1-bit input: Active-High B/Write port address enable
   CLKBWRCLK => CLKBWRCLK,             -- 1-bit input: B/Write port clock
   ENBWREN => ENBWREN,                 -- 1-bit input: Port B enable/Write enable
   REGCEB => REGCEB,                   -- 1-bit input: Port B register enable
   RSTRAMB => RSTRAMB,                 -- 1-bit input: Port B set/reset
   RSTREGB => RSTREGB,                 -- 1-bit input: Port B register set/reset
   WEBWE => WEBWE,                     -- 8-bit input: Port B write enable/Write enable
   -- Port B Data inputs: Port B data
   DINBDIN => DINBDIN,                 -- 32-bit input: Port B data/MSB data
   DINPBDINP => DINPBDINP              -- 4-bit input: Port B parity/MSB parity
);

-- End of RAMB36E2_inst instantiation

Verilog Instantiation Template


// RAMB36E2: 36K-bit Configurable Synchronous Block RAM
//           UltraScale
// Xilinx HDL Language Template, version 2021.1

RAMB36E2 #(
   // CASCADE_ORDER_A, CASCADE_ORDER_B: "FIRST", "MIDDLE", "LAST", "NONE"
   .CASCADE_ORDER_A("NONE"),
   .CASCADE_ORDER_B("NONE"),
   // CLOCK_DOMAINS: "COMMON", "INDEPENDENT"
   .CLOCK_DOMAINS("INDEPENDENT"),
   // Collision check: "ALL", "GENERATE_X_ONLY", "NONE", "WARNING_ONLY"
   .SIM_COLLISION_CHECK("ALL"),
   // DOA_REG, DOB_REG: Optional output register (0, 1)
   .DOA_REG(1),
   .DOB_REG(1),
   // ENADDRENA/ENADDRENB: Address enable pin enable, "TRUE", "FALSE"
   .ENADDRENA("FALSE"),
   .ENADDRENB("FALSE"),
   // EN_ECC_PIPE: ECC pipeline register, "TRUE"/"FALSE"
   .EN_ECC_PIPE("FALSE"),
   // EN_ECC_READ: Enable ECC decoder, "TRUE"/"FALSE"
   .EN_ECC_READ("FALSE"),
   // EN_ECC_WRITE: Enable ECC encoder, "TRUE"/"FALSE"
   .EN_ECC_WRITE("FALSE"),
   // INITP_00 to INITP_0F: Initial contents of parity memory array
   .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
   // INIT_00 to INIT_7F: Initial contents of data memory array
   .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
   // INIT_A, INIT_B: Initial values on output ports
   .INIT_A(36'h000000000),
   .INIT_B(36'h000000000),
   // Initialization File: RAM initialization file
   .INIT_FILE("NONE"),
   // Programmable Inversion Attributes: Specifies the use of the built-in programmable inversion
   .IS_CLKARDCLK_INVERTED(1'b0),
   .IS_CLKBWRCLK_INVERTED(1'b0),
   .IS_ENARDEN_INVERTED(1'b0),
   .IS_ENBWREN_INVERTED(1'b0),
   .IS_RSTRAMARSTRAM_INVERTED(1'b0),
   .IS_RSTRAMB_INVERTED(1'b0),
   .IS_RSTREGARSTREG_INVERTED(1'b0),
   .IS_RSTREGB_INVERTED(1'b0),
   // RDADDRCHANGE: Disable memory access when output value does not change ("TRUE", "FALSE")
   .RDADDRCHANGEA("FALSE"),
   .RDADDRCHANGEB("FALSE"),
   // READ_WIDTH_A/B, WRITE_WIDTH_A/B: Read/write width per port
   .READ_WIDTH_A(0),                                                                 // 0-9
   .READ_WIDTH_B(0),                                                                 // 0-9
   .WRITE_WIDTH_A(0),                                                                // 0-9
   .WRITE_WIDTH_B(0),                                                                // 0-9
   // RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG", "REGCE")
   .RSTREG_PRIORITY_A("RSTREG"),
   .RSTREG_PRIORITY_B("RSTREG"),
   // SRVAL_A, SRVAL_B: Set/reset value for output
   .SRVAL_A(36'h000000000),
   .SRVAL_B(36'h000000000),
   // Sleep Async: Sleep function asynchronous or synchronous ("TRUE", "FALSE")
   .SLEEP_ASYNC("FALSE"),
   // WriteMode: "WRITE_FIRST", "NO_CHANGE", "READ_FIRST"
   .WRITE_MODE_A("NO_CHANGE"),
   .WRITE_MODE_B("NO_CHANGE")
)
RAMB36E2_inst (
   // Cascade Signals outputs: Multi-BRAM cascade signals
   .CASDOUTA(CASDOUTA),               // 32-bit output: Port A cascade output data
   .CASDOUTB(CASDOUTB),               // 32-bit output: Port B cascade output data
   .CASDOUTPA(CASDOUTPA),             // 4-bit output: Port A cascade output parity data
   .CASDOUTPB(CASDOUTPB),             // 4-bit output: Port B cascade output parity data
   .CASOUTDBITERR(CASOUTDBITERR),     // 1-bit output: DBITERR cascade output
   .CASOUTSBITERR(CASOUTSBITERR),     // 1-bit output: SBITERR cascade output
   // ECC Signals outputs: Error Correction Circuitry ports
   .DBITERR(DBITERR),                 // 1-bit output: Double bit error status
   .ECCPARITY(ECCPARITY),             // 8-bit output: Generated error correction parity
   .RDADDRECC(RDADDRECC),             // 9-bit output: ECC Read Address
   .SBITERR(SBITERR),                 // 1-bit output: Single bit error status
   // Port A Data outputs: Port A data
   .DOUTADOUT(DOUTADOUT),             // 32-bit output: Port A Data/LSB data
   .DOUTPADOUTP(DOUTPADOUTP),         // 4-bit output: Port A parity/LSB parity
   // Port B Data outputs: Port B data
   .DOUTBDOUT(DOUTBDOUT),             // 32-bit output: Port B data/MSB data
   .DOUTPBDOUTP(DOUTPBDOUTP),         // 4-bit output: Port B parity/MSB parity
   // Cascade Signals inputs: Multi-BRAM cascade signals
   .CASDIMUXA(CASDIMUXA),             // 1-bit input: Port A input data (0=DINA, 1=CASDINA)
   .CASDIMUXB(CASDIMUXB),             // 1-bit input: Port B input data (0=DINB, 1=CASDINB)
   .CASDINA(CASDINA),                 // 32-bit input: Port A cascade input data
   .CASDINB(CASDINB),                 // 32-bit input: Port B cascade input data
   .CASDINPA(CASDINPA),               // 4-bit input: Port A cascade input parity data
   .CASDINPB(CASDINPB),               // 4-bit input: Port B cascade input parity data
   .CASDOMUXA(CASDOMUXA),             // 1-bit input: Port A unregistered data (0=BRAM data, 1=CASDINA)
   .CASDOMUXB(CASDOMUXB),             // 1-bit input: Port B unregistered data (0=BRAM data, 1=CASDINB)
   .CASDOMUXEN_A(CASDOMUXEN_A),       // 1-bit input: Port A unregistered output data enable
   .CASDOMUXEN_B(CASDOMUXEN_B),       // 1-bit input: Port B unregistered output data enable
   .CASINDBITERR(CASINDBITERR),       // 1-bit input: DBITERR cascade input
   .CASINSBITERR(CASINSBITERR),       // 1-bit input: SBITERR cascade input
   .CASOREGIMUXA(CASOREGIMUXA),       // 1-bit input: Port A registered data (0=BRAM data, 1=CASDINA)
   .CASOREGIMUXB(CASOREGIMUXB),       // 1-bit input: Port B registered data (0=BRAM data, 1=CASDINB)
   .CASOREGIMUXEN_A(CASOREGIMUXEN_A), // 1-bit input: Port A registered output data enable
   .CASOREGIMUXEN_B(CASOREGIMUXEN_B), // 1-bit input: Port B registered output data enable
   // ECC Signals inputs: Error Correction Circuitry ports
   .ECCPIPECE(ECCPIPECE),             // 1-bit input: ECC Pipeline Register Enable
   .INJECTDBITERR(INJECTDBITERR),     // 1-bit input: Inject a double-bit error
   .INJECTSBITERR(INJECTSBITERR),
   // Port A Address/Control Signals inputs: Port A address and control signals
   .ADDRARDADDR(ADDRARDADDR),         // 15-bit input: A/Read port address
   .ADDRENA(ADDRENA),                 // 1-bit input: Active-High A/Read port address enable
   .CLKARDCLK(CLKARDCLK),             // 1-bit input: A/Read port clock
   .ENARDEN(ENARDEN),                 // 1-bit input: Port A enable/Read enable
   .REGCEAREGCE(REGCEAREGCE),         // 1-bit input: Port A register enable/Register enable
   .RSTRAMARSTRAM(RSTRAMARSTRAM),     // 1-bit input: Port A set/reset
   .RSTREGARSTREG(RSTREGARSTREG),     // 1-bit input: Port A register set/reset
   .SLEEP(SLEEP),                     // 1-bit input: Sleep Mode
   .WEA(WEA),                         // 4-bit input: Port A write enable
   // Port A Data inputs: Port A data
   .DINADIN(DINADIN),                 // 32-bit input: Port A data/LSB data
   .DINPADINP(DINPADINP),             // 4-bit input: Port A parity/LSB parity
   // Port B Address/Control Signals inputs: Port B address and control signals
   .ADDRBWRADDR(ADDRBWRADDR),         // 15-bit input: B/Write port address
   .ADDRENB(ADDRENB),                 // 1-bit input: Active-High B/Write port address enable
   .CLKBWRCLK(CLKBWRCLK),             // 1-bit input: B/Write port clock
   .ENBWREN(ENBWREN),                 // 1-bit input: Port B enable/Write enable
   .REGCEB(REGCEB),                   // 1-bit input: Port B register enable
   .RSTRAMB(RSTRAMB),                 // 1-bit input: Port B set/reset
   .RSTREGB(RSTREGB),                 // 1-bit input: Port B register set/reset
   .WEBWE(WEBWE),                     // 8-bit input: Port B write enable/Write enable
   // Port B Data inputs: Port B data
   .DINBDIN(DINBDIN),                 // 32-bit input: Port B data/MSB data
   .DINPBDINP(DINPBDINP)              // 4-bit input: Port B parity/MSB parity
);

// End of RAMB36E2_inst instantiation

Related Information

  • See the UltraScale Architecture Memory Resources User Guide (UG573).