Some common examples of bus interfaces are buses that conform to the
AXI specification such as AXI4, AXI4-Lite and AXI4-Stream. The
interface includes all three subsets (AXI4, AXI3, and AXI4-Lite). Other
interfaces include block RAM.
I/O Bus Interfaces
Some bus interfaces that group a set of signals going to I/O ports are called I/O interfaces. Examples include: UART, I2C, SPI, Ethernet, PCI™ , and DDR.
Special signals include:
- Clock Enable
- Data (for traditional arithmetic IP which do not have any AXI interface, for example adders, subtractors, and multipliers)
These special signals are described in the following sections.
The clock interface can have the following parameters associated with them. These parameters are used in the design generation process and are necessary when the IP is used with other IP in the design.
ASSOCIATED_BUSIF: The list contains the names of all bus interfaces which run at this clock frequency. This parameter takes a colon-separated list (:) of strings as its value.
If there are no interface signals at the boundary that run at this clock rate, this field is left blank.Figure 1. ASSOCIATED_BUSIF
The figure shows the
ASSOCIATED_BUSIFparameter of the selected clock interface port lists the master interfaces (
M01_AXI) and slave interfaces (
S01_AXI) separated by colons.
If one of the interfaces, such as
M00_AXI, does not run at this clock frequency, leave the interface out of the
ASSOCIATED_BUSIFparameter for the clock.
ASSOCIATED_RESET: The list contains names of reset ports (not names of reset container interfaces) as its value. This parameter takes a colon-separated (:) list of strings as its value. If there are no resets in the design, this field is left blank.
ASSOCIATED_CLKEN: The list contains names of clock enable ports (not names of container interfaces) as its value. This parameter takes a colon-separated (:) list of strings as its value. If there are no clock enable signals in the design, this field is left blank.
FREQ_HZ: This parameter captures the frequency in hertz at which the clock is running in positive integer format. This parameter needs to be specified for all output clocks only.
PHASE: This parameter captures the phase at which the clock is running. The default value is 0. Valid values are 0 to 360. If you cannot specify the
PHASEin a fixed manner, then you must update it in bd.tcl, similar to updating
CLK_DOMAIN: This parameter is a string ID. By default, IP integrator assumes that all output clocks are independent and assigns a unique ID to all clock outputs across the block design. This is automatically assigned by IP integrator, or managed by IP if there are multiple output clocks of the same domain.
To see the properties on the clock net, select the source clock port or pin and analyze the properties on the object. The following figure shows the Clocking Wizard and the clock properties on the selected pin.
You can also double-click a port or pin to see the customization dialog box for the selected object.
This container bus interface includes the
POLARITY parameter. Valid values for this
ACTIVE_LOW. The default is
To see the properties on the reset net, select the reset port or pin and analyze the properties on the object, as shown in the following figure.
The following figure shows the Properties window.
This bus interface includes the parameter,
SENSITIVITY: Valid values for this parameter are
EDGE_FALLING. The default is
To see the properties on the interrupt pin, highlight the pin, and look at the properties window, as shown in the following figure.
There are two parameters associated with Clock Enable: