UltraScale architecture-based devices provide the capability to cascade the data out from one block RAM to the next block RAM serially. This will enable the devices to create a deeper block RAM in a bottom-up fashion. When used in cascaded mode, the power consumption is considerably low compared to the block RAM used in non-cascaded mode.
- Run the steps mentioned in Step 1 shown in Lab
- In the Add Source Files dialog box, add the source files in the <Extract_Dir>/UltraScale/src for UltraScale devices.
- In the Add Constraints (optional) page, click Add Files and select dut_fpga_kcu105.xdc in the file browser. In the directory structure, you will find the dut_fpga_kcu105.xdc file below the /src folder.
- Select the Kintex UltraScale KCU105 Evaluation Platform (xcku040-ffva156-2-e FPGA), click Next.
- Review the New Project Summary page. Verify that the data appears as expected and click Finish.
- In the Vivado Settings dialog box ( ), enter the tutorial project directory in the Specify project directory box, so that all reports are saved in the tutorial project directory. Then click OK.
- Click Run Synthesis in the Flow Navigator.
The Synthesis Completed dialog box appears after synthesis has completed on the design.
- Select Run Implementation in the Synthesis Completed dialog box and click OK.
- After the Implementation completes, click Open Implemented Design.
- You can see the automatically generated power report impl_1 in the Power window, which shows as a saved report. This is an autogenerated vectorless power report.
- Note the total power (Total On-Chip
Power) in the power report Summary view.
- Select Hierarchical view under
Utilization Details on the left panel
and observe the cascaded and non-cascaded block RAM power.
- You can see 50% to 60% saving in cascaded block RAM compared to non-cascaded block RAM.
- Use the same steps as specified in Step 1, Step 2, and Step 3 to perform SAIF based power analysis using Vivado Simulator.