Customizing the VCU DDR4 Controller - 2021.2 English

H.264/H.265 Video Codec Unit v1.2 Solutions LogiCORE IP Product Guide (PG252)

Document ID
PG252
Release Date
2021-10-27
Version
2021.2 English

You can customize the GUI based on the following options:

Ref Clk (MHz)
This is a user defined clock that varies from 75MHz to 770MHz.
Choose RAM
You can select from "BRAM" or "URAM + BRAM". Note that for 4EV and 5EV devices, the "URAM + BRAM" option is not valid. For 7EV devices, you should be aware that additional IPs in the design can consume URAMs and may result in a overutilization of URAMs in the 7EV device.
DRAM speed bin selection
2133 and 2400 for x8 selection. 2400 and 2667 for x16 selection.
Figure 1. GUI Configuration

The port priority is fixed. Five ports are enabled in the IP. The high priority ports need to be connected to a decoder/display interface. The low priority ports need to be connected to a PS, Micro Controller Unit (MCU) interface.

Custom Flow

In the current VCU, DDR4 logic core IP supports only listed memories. and If additions are required, the user needs to get support from Xilinx team to add the new memories. To avoid this scenario, the VCU DDR4 controller is enhanced to support custom memory addition by getting the parameters and CSV format such as MIG input.

The following figure shows the GUI changes:

Figure 2. Custom Flow GUI Configuration

The preceding figure shows the GUI with updated DDR4 controller.

To add memory, perform the following steps:

  1. Check the Enable Custom Parts option
  2. Set the Reference clock (Ref clk (MHZ)). Currently, the Reference clock is  user configurable from 75Mhz to 770Mhz.
  3. Select the Data rate (Data Rate (MT/s)) from DDR4-2133, DDR4-2400 and DDR4 -2667.
  4. Select the DIMM Type from SODIMM and COMPONENT
  5. Select the populated CSV file in (Custom Parts Data File). (Details about the CSV file are explained in the following section.)
  6. Select the Phy clock which is again user configurable. For better performance, select between 200 to 375 MHz.

Remaining parts are not required for the custom flow.

CSV File Detailss

Note that the CSV file needs to have only two rows - the first row contains the parameter names, and the second row contains only values.

The following are the valid values for all the parameters

  • Rank is limited to 2.
  • Stack Height is limited to 1.
  • CA Mirror is limited to 0.
  • Data mask is limited 1.
  • Address width is limited to 17.
  • Row width is limited to 14, 15, 16, 17, or 18.
  • Column width is limited to 10.
  • Bank width is limited to 2. (Listed as Bank address in a bank group for Micron parts).
  • Bank Group width is limited to 1 for x16 devices and 2 for x4/x8 devices. (Listed as Bank group address in Micron parts).
  • CS width is limited to 1 or 2 for components and DIMMs, and 2 or 4 for LRDIMMs.
  • CKE width is limited to 1 and 2.
  • ODT width is limited to 1 and 2.
  • CK width is limited to 1 and 2.
  • Memory Speed grade is limited to the value defined in the memory vendor data sheet.
    Note: This value is for information purposes only and is not used by the IP
  • Memory density is limited to the value defined in the memory vendor data sheet.
    Note: This value is for information purposes only and is not used by the IP.
  • Component density is limited to the value defined in the memory vendor data sheet.
    Note: This value is for information purposes only and is not used by the IP.
  • Memory device width is limited to 4, 8, or 16 for components, and 64 or 72 for DIMMs.
  • Memory component width is limited to 4, 8, and 16.
  • Data bits per strobe is limited to 4 and 8.
  • I/O Voltage is limited to 1.2V.
  • Data width is limited to 8, 16, 24, 32, 40, 48, 56, 64, 72, 80.
    Note: Data width is limited to a maximum of 9 components.
  • Min period has a range between 750ps and 1600ps.
  • Max period is limited to 1600ps.
  • tCKE is limited to 5000ps.
  • tFAW is limited to 10000-35000ps.
    Note: This value often has a range that varies with frequency. It is critical that this is entered correctly based on the target memory interface rate.
  • tFAW_dllr is limited to 16 tck.
    Note: This parameter is only used for 3DS parts and should be set to 0 when using non-3DS parts.
  • tMRD is limited to 8-10tck.
  • tRAS is limited to 32000-35000ps.
  • tRCD is limited to12500-15000ps.
  • tREFI is limited to 3900000-7800000ps.
  • tRFC is limited to 90000-550000ps.
  • tRFC_dlr is limited to 90000-120000 ps.
    Note: This parameter is only used for 3DS parts and should be set to 0 when using non-3DS parts.
  • tRP is limited to 12500-15000ps.
  • tRRD_S is limited to 2500-6000ps.
    Note: This value often has a range that varies with frequency. It is critical that this is entered correctly based on the target memory interface rate.
  • tRRD_L is limited to 4900-7500ps.
    Note: This value often has a range that varies with frequency. It is critical that this is entered correctly based on the target memory interface rate.
  • tRRD_dlr is limited to 4 tck.
    Note: This parameter is only used for 3DS parts and should be set to 0 when using non-3DS parts.
  • tRTP is limited to 7500ps.
  • tWR is limited to 15000ps.
  • tWTR_S is limited to 2500ps.
  • tWTR_L is limited to 7500ps.
  • tXPR is limited to 100-560ns.
    Note: This value often has a range that varies with frequency. It is critical that this is entered correctly based on the target memory interface rate.
  • tZQCS is limited to 128tck.
  • tZQINIT is limited to 1024tck.
  • tCCD_3ds is limited to 4-5 tck.
    Note: This parameter is only used for 3DS parts and should be set to '0' when using non-3DS parts.
  • CAS Latency is limited to 9 to 24 but specific values can be obtained from the memory vendor data sheet.
    Note: This value often has a range that varies with frequency. It is critical that this is entered correctly based on the target memory interface rate.
  • CAS Write Latency has a range between 9 to 20 but specific values can be obtained from the memory vendor data sheet.
    Note: This value often has a range that varies with frequency. It is critical that this is entered correctly based on the target memory interface rate.
  • Burst Length is limited to 8.
  • RTT (nominal) - ODT is limited to RZQ/6.
    Note: This parameter has been removed starting in the 2016.4 example CSV as the IP automatically defines this value based on slot and rank selection.