AI Engine Simulation-Based Profiling - 2021.2 English

Versal ACAP AI Engine Programming Environment User Guide (UG1076)

Document ID
UG1076
Release Date
2021-12-17
Version
2021.2 English

Profiling data generation

In the simulation framework, the AI Engine simulator can generate a profiling report for the complete application. This report is generated using the flag –profile.

aiesimulator –pkg-dir=Work –profile

Text files and xml files are generated in the directory aiesimulator_output. Two types of files are generated for the tile located in column C and row R. The *_funct reports the number of calls and number of cycles for each function. The *_instr is a report that goes down to the assembly code. To visualize the report, use the Vitis analyzer.

vitis_analyzer aiesimulator_output/default.aierun_summary
The Profile tab opens the Profile report, which shows a menu of sections that show information.
Summary
Reports the total cycle count, total instruction count, and program size in memory.
Function Reports
Shows several key indicators, function by function, in a table and graphs.
  • Number of calls
  • Total function time (cycles and %)
  • Total function + descendant time (cycles and %)
  • Min/Avg/Max function time (cycles)
  • Min/Avg/Max function + descendant time (cycles)
  • Program counter Low/High
Profile Details
Shows the assembly code, function by function, with useful precisions. The columns are as shown in the following table.
Table 1. Profile Details Column Description
Column Name Content
PC Program counter
Instruction Up to 16 bytes for each line
Assembly Assembly code mnemonic with the full 7-way instruction word
Exe-count Number of times this line has been executed by the processor
Cycles Number of cycles required
User Count
Wait States For some instructions you may have memory conflicts which end up into a number of wait-states
Relative cycle use within function Shown as ‘*’ lines where the relative length visually shows the relative cycles use of this instruction within the function
Relative cycle use within simulation Shown as ‘*’ lines where the relative length visually shows the relative cycles use of this instruction within the simulation (including main() and all functions)
Relative wait-state use within function Shown as ‘W’ lines where the relative length visually shows the relative cycles used by wait-states during this instruction within the function
Relative wait state use within simulation Shown as ‘*’ lines where the relative length visually shows the relative cycles used by wait states during this instruction within the simulation (including main() and all functions)

Performance Debug with Profiling Data

Performance improvement of a design should start by optimizing the function that takes most of the cycles. After it is done, you can optimize functions that take less and less proportion of the cycles. For this purpose, the total function time graph will help you in selecting these functions.

For the optimization itself, you can use pragmas (chess_prepare_for_pipelining, chess_loop_range) for the usual pipelining, unrolling of loops. The Profile Details tab provides insight about wait states. Even if your inner-loop is perfectly optimized, you may lose some cycles due to wait-states. These wait-states occur when there are conflicts in resource access.

  • Two reads or one read and one write within the same memory bank, either from the local AI Engine, or two contiguous AI Engines.
  • The local AI Engine tries to access a bank (either read or write) while a memory DMA is accessing it for some data transfer.

Here is an example of profile details.