You can change the peripheral operation frequency by directly setting the frequency in the corresponding peripheral clock configuration register. The Zynq UltraScale+ MPSoC BSP provides APIs that aid in changing the peripheral clock frequency dynamically according to your requirements.
The following table shows the standalone APIs that can be used to change the frequency of the peripherals
| APIs | Description |
|---|---|
| XSDPS_change_clkfreq | Change the clock frequency of SD. |
| XSPIPS_setclkprescaler XSPIPS_getclkprescaler | Pre-scale the SPI frequency. |
| XRtcPSu_calculatecalibration | Change the oscillator frequency. |
| XQSPIPSU_setclkprescaler | Change the clock frequency of QSPI. |
In case of a Linux application, the frequency of all the peripherals is set in the device tree file. The following code snippet shows the setting of peripheral clock.
ps7_qspi_0: ps7-qspi:dir0xFF0F0000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
#bus-cells = <0x1>;
clock-names = “ref_clk”, “pclk”;
compatible = “xlnx,usmp-gqspi”, “cdns,spi-r1p6”; stream-connected-dma = <0x26>;
clocks = <0x1e 0x1e>; dma = <0xb>; interrupts = <0xf>;
num-chip-select = <0x2>;
reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>;
speed-hz = <0xbebc200>; xlnx,fb-clk = <0x1>;
xlnx,qspi-clk-freq-hz = <0xbebc200>; xlnx,qspi-mode = <0x2>;
To avoid any error condition, the peripheral needs to be stopped before changing the corresponding clock frequency.
The steps to follow before changing the clock frequency for any peripheral are as follows:
- Stop the transition pertaining to the peripheral (IP) and make it idle.
- Stop the IP by appropriately configuring the registers.
- Change the clock frequency of the peripheral.
- Issue soft reset to the IP.
- Restart the IP.
For more information on Zynq UltraScale+ MPSoC clock generator, see this link in the “Clocking” chapter in the in the Zynq UltraScale+ Device Technical Reference Manual (UG1085).