The DDR controller implements the following mechanisms to reduce its power consumption:
- Clock Stop
- When enabled, the DDR PHY can stop the clocks to the DRAM.
- For DDR2 and DDR3, this feature is only effective in self-refresh mode.
- For LPDDR2, this feature becomes effective during idle periods, power-down mode, self-refresh mode, and deep power-down mode.
- Pre-Charge Power Down
- When enabled, the DDRC dynamically uses pre-charge power down mode to reduce power consumption during idle periods. Normal operation continues when a new request is received by the controller.
- The DDR controller can dynamically put the DRAM into self-refresh mode during
idle periods. Normal operation continues when a new request is received by the
In this mode, DRAM contents are maintained even when the DDRC core logic is fully powered down; this allows stopping the DDR3X clock and the DCI clock that controls the DDR termination.