The Zynq® UltraScale+™ MPSoC has a serial input/output unit (SIOU) for a high-speed serial interface. It supports protocols such as PCIe® , USD 3.0, DisplayPort, SATA, and Ethernet protocols.
- The SIOU block is part of the full-power domain (FPD) in the PS.
- The USB and Ethernet controller blocks that are part of the low-power domain (LPD) in the Zynq UltraScale+ MPSoC also share the PS-GTR transceivers.
- The interconnect matrix enables multiplexing of four PS-GTR transceivers in various combinations across multiple controller blocks.
- A register block controls or monitors signals within the SIOU.
This chapter explains the configuration flow of the high-speed interface protocols.
See this link to the “High-Speed PS-GTR Transceiver Interface” of the Zynq UltraScale+ Device Technical Reference Manual (UG1085) for more information.