The heterogeneous nature and performance of the Versal ACAP necessitates a system-level high-bandwidth debug and trace solution. The high-speed debug port (HSDP) is a new feature in Versal ACAP that provides unified, at-speed debugging and tracing of the various integrated, fabric-based, and processor blocks in the device under test (DUT). HSDP provides the option of performing debug and trace capture through a dedicated Aurora interface and a high-speed debug cable like SmartLynq+. High-speed debug over PCIe is also available for remote systems that are connected to a host through PCIe.
For more information, see the following resources:
- This link in the Versal ACAP Technical Reference Manual (AM011)
- SmartLynq+ Module User Guide (UG1514)
- System Design Example for High-Speed Debug Port with SmartLynq+ Module