Revision History - 2021.2 English

Versal ACAP Design Guide (UG1273)

Document ID
Release Date
2021.2 English

The following table shows the revision history for this document.

Section Revision Summary
10/27/2021 Version 2021.2
Using the Vitis Environment in the Design Flows Added link to Model Composer tutorials and examples on GitHub.
Logic Simulation Using SystemC Models Removed CPM table row.
System Debug Added information on PJTAG.
Security Removed redundant Authentication + Decryption table row.
Classic SoC Boot Added link to more information on Dynamic Function eXchange (DFX).
09/03/2021 Version 2021.1
Performance and PL Maximum Frequency Added new section.
06/30/2021 Version 2021.1
HSDP Added additional resources.
System Design Types Revised traditional and platform-based design flows summary.
Platform-Based Design Flows Updated main steps.
Block Design Flow Updated IP integrator requirement.
Apply Constraints and Implement Design Added tip about power rail constraints.
Using the Vitis Environment in the Design Flows Updated description of platform, subsystem, and software application.
Vitis Processing Systems Design Methodology Updated final integration and test methodology.
Assembly and Simulation Using Hardware Emulation Updated PS program information.
Logic Simulation Using SystemC Models Added CIPS VIP.
Power and Error Handling Added information on the error aggregation module (EAM).
Security Added information on BootROM and link to Versal ACAP Security Manual (UG1508).
Boot and Configuration Added Zynq UltraScale+ RFSoC designs.
Classic SoC Boot Added new section.
PL Configuration and JTAG Added information on ICAPE3.