When you migrate designs to Versal® ACAP from the UltraScale™ or UltraScale+™ architectures, the Xilinx® tools can only automatically migrate some of the PL primitives and integrated IP blocks. In some cases, there is no equivalent functionality or connectivity in Versal® devices. Although partial migration might be possible, this approach generally leads to sub-optimal hardware and application performance. Therefore, Xilinx recommends using the following steps instead:
- Rearchitect any high-bandwidth connections between major blocks to use the NoC instead of the PL-based AXI Interconnect or similar IP.
- Reduce PL logic by leveraging all new integrated blocks, such as the integrated memory controller, DMA, and AI Engine.
- Replace instantiated PL primitives from previous architectures with the equivalent RTL descriptions or XPMs (e.g., memory blocks, DSPs, carry logic, multiplexers, etc.).
- Regenerate or recreate all IP blocks.
- Resynthesize the complete design instead of migrating netlists created for previous architectures.
Any portion of the design that is automatically migrated must be carefully reviewed to ensure that the application's performance, resource, and power will be met. For designs migrated from Zynq® UltraScale+™ MPSoCs, Xilinx recommends recreating the PS functions and connectivity by instantiating the CIPS IP in a new design instead of attempting migration via tools automation.
The following table shows the blocks and functionality for which automatic migration is available.
|Configurable logic block (CLB)||Yes|
|On-chip memory (OCM) resources (block RAM and UltraRAM)||Most|
|Soft memory controllers||No|
|Processor and peripherals||No|
|System monitor (SYSMON)||No|
|Power and error handling||No|
|Boot and configuration||No|
|PL configuration and JTAG||No|
For designs migrating from Kintex® UltraScale™ , Kintex UltraScale+, Virtex® UltraScale™ , or Virtex UltraScale+ devices, the CIPS IP must be added to enable essential functionality, such as device configuration and hardware debug features, even if the PS features are not used. Other designs migrating from Zynq UltraScale+ MPSoCs are expected to already have a PS block. For more information about the CIPS IP, see the Control, Interface and Processing System LogiCORE IP Product Guide (PG352).