Using the Vitis Environment in the Design Flows - 2021.2 English

Versal ACAP Design Guide (UG1273)

Document ID
Release Date
2021.2 English

Versal ACAP designs are enabled by the Vitis tools, libraries, and IP. The Vitis environment lets you program, run, and debug the different elements of a Versal ACAP application, which can include AI Engine kernels and graphs, PL, high-level synthesis (HLS) IP, RTL IP, and PS applications. Each domain has its own set of tools and methodologies. For more information, see the Vitis Unified Software Platform Documentation (UG1416).

The following Vitis environment tools and flows facilitate the assembly of PS, PL, and AI Engine components to create processing systems, which are then integrated with a platform:

AI Engine tools
Program, debug, and deploy graph algorithms, including the aiecompiler, SystemC simulator (aiesimulator), and x86 simulator (x86simulator).
Vitis HLS and Vitis compiler (v++ --compile)
Creates PL kernels from C/C++ source code.
Vivado IP packager
Packages existing IP or RTL code into Vitis PL kernels.
Vitis linker (v++ --link)
Integrates AI Engine graphs and PL kernels into a platform.
Vitis embedded software development flow (with the system software stack including PetaLinux)
Provides support for the PS domain of the embedded processor.
Vitis packager (v++ --package)
Integrates the PS components of the system and generates the boot image.
Vitis emulation flow
Simulates the behavior of the PS, PL, and AI Engine components after integration with the Vitis linker and prior to running on actual hardware.
Note: Model Composer is also available for users familiar with MATLABĀ® software. For more information, see the Vitis Model Composer User Guide (UG1483) and the Vitis Model Composer Examples and Tutorials.

The Vitis tools use a platform-based approach in which the system is conceptually divided into the following elements: the platform, the processing system, and the software application. This design approach with well-defined design elements promotes concurrent development and delivers higher productivity.

Provides the foundational hardware IP blocks and software features upon which the processing system and software application can be built and integrated.
Processing System
Consists of PS, PL, and optional AI Engine features that implement the main functionality of the system.
Software application
Runs on the PS and performs high-level application tasks while interacting with the processing system.


Platforms comprise two parts: the hardware platform and the software platform. The hardware platform contains the foundational Versal hardware IP blocks, including CIPS, NoC, I/O controllers, AI Engine array, and other user-specified IP blocks. The software platform defines the domains, device tree, and OS.

The platform insulates application developers from the details of the low-level infrastructure and lets them focus on development of a specific functions of the processing system, such as software, AI Engine graph, or PL kernel logic.

You can develop custom platforms using the Vivado tools in parallel with the processing system, which you develop using the Vitis tool flow. For information on platform creation using the Vivado tools, see Creating and Generating Platforms.

Processing Systems

Processing systems perform well-defined functions, leveraging PS firmware, PL kernels, and optionally AI Engine graphs. The components of a processing system are individually designed and verified before being assembled and integrated with a platform using the Vitis linker.

Xilinx recommends that developers start their work by targeting a standard Xilinx platform before transitioning to a custom platform developed for a specific board and application. This approach reduces risk and uncertainty and increases the chances of success when integrating the subsystem with the custom platform.