DFX Usage and NoC Clock Gating - 2021.2 English

Xilinx Power Estimator User Guide for Versal ACAP (UG1275)

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Release Date
2021.2 English

The state of NoC clock gating enabled/disabled i.e. number of used NoC clock buffers are dependent of the DFX usage of the design. The mode of DFX used can be selected from DFX Usage section of the Summary Tab.

NoC clock gating can only be enabled if DFX is unused or only 1 reconfigurable partition (RP) is used in the design. This setting is with respect to the NoC containing elements in the RP, if the NoC is static for all RPs then select DFX is unused. If 2 or more RPs are used that contain NoC elements then NoC clock gating is disabled, this means all NoC clock buffers are turned on, XPE then accounts for the additional NoC clock power in the VCC_SOC rail. Following is the detailed description of each mode:

No DFX, or no RPs include NoC resources (Default)
Select this option if DFX is not used in your design or if DFX is being used but none of the RPs contain NoC resources.
Classic SoC Boot mode
This mode allows users to configure the PS and System Domains and boot Linux, before the PL. To enable this mode a single DFX RP is used for the PL. You must connect an external memory via the SYSTEM domain. NoC clock gating is still possible, but you must specify the DDRMC and NoC paths you plan to use in the NoC_DDRMC tab for XPE to correctly estimate the SYSTEM domain power.
DFX with 1 RP that includes NoC resources
Select this setting when using DFX and if there is 1 RP that contains NoC resources
DFX with 2 or more RPs with NoC resources
When 2 or more RPs contain NoC resources, NoC clock gating is not possible, select this option to allow XPE to correctly account for the additional VCC_SOC power.