I/O Sheet - 2021.2 English

Xilinx Power Estimator User Guide for Versal ACAP (UG1275)

Document ID
Release Date
2021.2 English

With higher switching speeds and capacitive loads, switching I/O power can be a substantial part of the total power consumption of a Xilinx® device. Because of this, it is important to accurately define all I/O related parameters. In the I/O sheet, XPE helps you calculate the on-chip and off-chip power for your I/O interfaces. XPE provides a Memory Interface Configuration wizard to allow you to quickly enter the important parameters required for an accurate power estimate of the I/Os involved in the device’s interface to external memory. For step-by-step instructions about how to use the wizard to fill out the memory interface information in the I/O sheet, use the Using the Soft Memory Interface Configuration Wizard.

The following figure illustrates the three main types of information entered on the I/O sheet: I/O Settings, Activity, and External Termination:

Figure 1. I/O Sheet
The following section provides more information on how to fill in each of these columns.
I/O Setting
  • I/O Standard: Specify here the expected I/O standard you will use for this interface. Configurations which use the on-chip terminations are shown with a DCI suffix in this drop-down menu. Differential I/O standards have a (pair) suffix. For calculations, XPE assumes the standard VCCO level (for example, 3.3V) that is closest to the nominal listed in the data sheet for that I/O standard.
  • I/O Direction Columns: Enter the number of Input, Output and Bidir (bidirectional) signals for each I/O interface.
    Tip: Enter one pin for each differential I/O pair. For example, if your memory has four differential DQS pairs, enter 4 on the Input Pins column.
  • On-Chip Termination: The termination values are same as that of UltraScale+ devices.
Enter in the expected activity for each I/O interface in the following columns.
  • Clock (MHz):
    Synchronous signals
    Enter the frequency of the clock capturing or generating these signals.
    Asynchronous signals
    Calculate the equivalent frequency of the signal. For example, if you can determine if the signal will toggle (change state) 2 million times per second then enter 1 in this column (when converting signal rate to frequency you need 2 transitions to make a period: the transition from 0 to 1 and the transition from 1 to 0).
Toggle Rate
Synchronous elements
Enter how often compared to the clock this signal is expected to change state. For example, if the data changes every 8 clock cycles on average, enter 12.5% (1/8, converted to a percentage).
Asynchronous elements
As explained in the Clock (MHz) description above, enter the equivalent frequency in the Clock (MHz) column and then enter 100% in this column.
Data Rate
Synchronous elements
Enter DDR if the signal is sampled on both the positive and negative edges of the clock. Enter SDR if the signal is sampled on only one edge of the clock.
Note: When the Data Rate is DDR, the specified toggle rate is doubled internally for power estimation. You must not calculate the toggle rate explicitly for double data rate.
Asynchronous elements and Clocks
Enter Async or Clock.
Output Enable
Input only signals
This column has no effect.
Output and bidirectional signals
Specify for a long period of time how much of this time the output buffer is driving a value (compared to the time the driving buffer is disabled or tri-stated.)
Tip: Setting Output Enable to 100% is a common mistake which degrades the XPE accuracy.
Term Disable
Set DCI or IOB33 OCT to disabled (DCITERMDISABLE) when not in use in the fabric. Enter the percentage of time the DCI or ICT termination is disabled.
IBUF Disable
Set HSTL/SSTL IBUF to low power idle (IBUFDISABLE) when not in use in the fabric. Enter the percentage of time the IBUF is disabled.
Output Load
Enter the power factor for the board and other external capacitance driven by the outputs in the module.
External Termination
When not using the available on-chip termination you can use XPE to calculate the power supplied by the Xilinx® device to off-chip components such as external board termination resistor networks. Multiple termination types are supported for I/Os configured as outputs. External input terminations are not supported, because calculations often require details of the driver side but these details are not available to XPE.