Slice Clock Enable - 2021.2 English

Xilinx Power Estimator User Guide for Versal ACAP (UG1275)

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2021.2 English

The Slice Clock Enable setting is used to reduce activity based on clock enables. Although the clock enable is functionally associated with logical registers, the majority of power attributed to register activity is due to the clock networks driving the registers. The clock power for registers, SRLs, and LUTRAMs are reported in clock sheet, based on the clock enable attribute. This is why the Slice Clock Enable setting appears on the Clock sheet rather than on the Logic sheet.