Primitive: Input Buffer With Input Buffer Disable and On-die Input Termination Disable
- PRIMITIVE_GROUP: I/O
- PRIMITIVE_SUBGROUP: INPUT_BUFFER
The IBUF_INTERMDISABLE primitive is available in the HD I/O banks and is similar to the IBUF_IBUFDISABLE primitive in that it has a IBUFDISABLE port that can be used to disable the input buffer during periods that the buffer is not being used. The USE_IBUFDISABLE attribute must be set to TRUE and SIM_DEVICE to the appropriate value for this primitive to have the expected behavior specific to the architecture. The IBUF_INTERMDISABLE primitive also has an INTERMDISABLE port that can be used to disable the optional on-die receiver termination feature.
The IBUF_INTERMDISABLE primitive can disable the input buffer and force the O output to the internal logic to a logic-Low when the IBUFDISABLE signal is asserted High. The IBUF_INTERMDISABLE primitive further allows the termination legs to be disabled whenever the INTERMDISABLE signal is asserted High. These features can be combined to reduce power whenever the input is idle. Input buffers that use the VREF power rail (such as SSTL and HSTL) benefit the most from the IBUFDISABLE signal being set to TRUE because they tend to have higher static power consumption than the non-VREF standards such as LVCMOS and LVTTL.
I/O attributes that do not impact the logic function of the component, such as IOSTANDARD and IBUF_LOW_PWR, should be supplied to the top-level port via an appropriate property. For details on applying such properties to the associated port, see the Vivado Design Suite Properties Reference Guide (UG912).
|I||Input||1||Input port connection. Connect directly to top-level port in the design.|
|IBUFDISABLE||Input||1||Disables input path through the buffer and forces to a logic Low. This feature is generally used to reduce power at times when the I/O is idle for a period of time.|
|INTERMDISABLE||Input||1||Control to enable/disable of on-chip input termination. This is generally used to reduce power in long periods of an idle state.|
|O||Output||1||Buffer output representing the input path to the device.|
Design Entry Method
|IP and IP Integrator Catalog||No|
|SIM_DEVICE||STRING||"VERSAL_PRIME", "VERSAL_PRIME_ES1", "VERSAL_PRIME_ES2"||"7SERIES"||Set the device version for simulation functionality.|
|USE_IBUFDISABLE||STRING||"TRUE", "FALSE"||"TRUE"||Set this attribute to "TRUE" to enable the IBUFDISABLE pin.|
VHDL Instantiation Template
Library UNISIM; use UNISIM.vcomponents.all;
-- IBUF_IBUFDISABLE: Input Buffer With Input Buffer Disable -- Versal Prime series -- Xilinx HDL Language Template, version 2021.2 IBUF_IBUFDISABLE_inst : IBUF_IBUFDISABLE generic map ( SIM_DEVICE => "VERSAL_PRIME", -- Set the device version for simulation functionality (VERSAL_PRIME, -- VERSAL_PRIME_ES1) USE_IBUFDISABLE => "TRUE" -- Enable/Disable the IBUFDISABLE pin (FALSE, TRUE, T_CONTROL) ) port map ( O => O, -- 1-bit output: Buffer output I => I, -- 1-bit input: Buffer input (connect directly to top-level port) IBUFDISABLE => IBUFDISABLE -- 1-bit input: Buffer disable input, high=disable ); -- End of IBUF_IBUFDISABLE_inst instantiation
Verilog Instantiation Template
// IBUF_IBUFDISABLE: Input Buffer With Input Buffer Disable // Versal Prime series // Xilinx HDL Language Template, version 2021.2 IBUF_IBUFDISABLE #( .SIM_DEVICE("VERSAL_PRIME"), // Set the device version for simulation functionality (VERSAL_PRIME, // VERSAL_PRIME_ES1) .USE_IBUFDISABLE("TRUE") // Enable/Disable the IBUFDISABLE pin (FALSE, TRUE, T_CONTROL) ) IBUF_IBUFDISABLE_inst ( .O(O), // 1-bit output: Buffer output .I(I), // 1-bit input: Buffer input (connect directly to top-level port) .IBUFDISABLE(IBUFDISABLE) // 1-bit input: Buffer disable input, high=disable ); // End of IBUF_IBUFDISABLE_inst instantiation
- Versal ACAP SelectIO Resources Architecture Manual (AM010)