RAM64M - 2021.2 English

Versal Architecture Prime Series Libraries Guide (UG1344)

Document ID
UG1344
Release Date
2021-10-22
Version
2021.2 English

Primitive: 64-Deep by 4-bit Wide Multi Port Random Access Memory (Select RAM)

  • PRIMITIVE_GROUP: CLB
  • PRIMITIVE_SUBGROUP: LUTRAM

Introduction

This design element is a 64-bit deep by 4-bit wide, multi-port, random access memory with synchronous write and asynchronous independent bit wide read capability. This RAM is implemented using the LUT resources of the device (also known as SelectRAM™+) and does not consume any of the block RAM resources of the device. The RAM64M component is implemented in a single slice, and consists of one 4-bit write, 1-bit read port, and three separate 1-bit read ports from the same memory allowing for 4-bit write and independent bit read access RAM.
  • If the DIA, DIB, DIC, and DID inputs are all tied to the same data inputs, the RAM can become a 1 read/write port, 3 independent read port 64x1 quad port memory.

  • If DID is grounded, DOD is not used.

  • If ADDRA, ADDRB, and ADDRC are tied to the same address, the RAM becomes a 64x3 simple dual port RAM.

  • If ADDRD is tied to ADDRA, ADDRB, and ADDRC, the RAM is a 64x4 single port RAM.

There are several other possible configurations for this RAM.

Port Descriptions

Port Direction Width Function
DOA Output 1 Read port data outputs addressed by ADDRA
DOB Output 1 Read port data outputs addressed by ADDRB
DOC Output 1 Read port data outputs addressed by ADDRC
DOD Output 1 Read/Write port data outputs addressed by ADDRD
DIA Input 1 Write data inputs addressed by ADDRD (read output is addressed by ADDRA)
DIB Input 1 Write data inputs addressed by ADDRD (read output is addressed by ADDRB)
DIC Input 1 Write data inputs addressed by ADDRD (read output is addressed by ADDRC)
DID Input 1 Write data inputs addressed by ADDRD
ADDRA Input 6 Read address bus A
ADDRB Input 6 Read address bus B
ADDRC Input 6 Read address bus C
ADDRD Input 6 4-bit data write port, 1-bit data read port address bus D
WE Input 1 Write Enable
WCLK Input 1 Write clock (reads are asynchronous)

Design Entry Method

Instantiation Yes
Inference Recommended
IP Catalog No

This element can be inferred by some synthesis tools by describing a RAM with a synchronous write and asynchronous read capability. Consult your synthesis tool documentation for details on RAM inference capabilities and coding examples. Xilinx suggests that you instantiate this component if you have a need to implicitly specify the RAM function, or if you need to manually place or relationally place the component.

If synchronous read capability is desired, the outputs can be connected to an FDRE/FDSE (FDCE/FDPE if asynchronous reset is needed) in order to improve the output timing of the function. However, this is not necessary for the proper operation of the RAM. If you want to have the data clocked on the negative edge of a clock, an inverter can be described on the clock input to this component. This inverter will be absorbed into the block during implementation and set as the IS_WCLK_INVERTED attribute giving the ability to write to the RAM on falling clock edges.

If instantiated, the following connections should be made to this component:
  • Connect the WCLK input to the desired clock source, the DIA, DIB, DIC

  • Connect the DIA, DIB, DIC, and DID inputs to the data source to be stored

  • Connect the DOA, DOB, DOC, and DOD outputs to an FDCE D input or other appropriate data destination, or leave unconnected if not used

  • Connect the WE clock enable pin to the proper write enable source in the design

  • Connect the ADDRD bus to the source for the read/write addressing

  • Connect the ADDRA, ADDRB, and ADDRC buses to the appropriate read address connections

The optional INIT_A, INIT_B, INIT_C and INIT_D attributes let you specify the initial memory contents of each port using a 64-bit hexadecimal value. The INIT value correlates to the RAM addressing by the following equation: ADDRy[z] = INIT_y[z]. For instance, if the RAM ADDRC port is addressed to 00001, then the INIT_C[1] values would be the initial values shown on the DOC port before the first write occurs at that address. If left unspecified, the initial contents will default to all zeros.

Available Attributes

Attribute Type Allowed Values Default Description
INIT_A HEX Any 64-bit value All zeros Specifies the initial contents of the RAM on port A.
INIT_B HEX Any 64-bit value All zeros Specifies the initial contents of the RAM on port B.
INIT_C HEX Any 64-bit value All zeros Specifies the initial contents of the RAM on port C.
INIT_D HEX Any 64-bit value All zeros Specifies the initial contents of the RAM on port D.
IS_WCLK_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the WCLK pin.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- RAM64M: 64-deep by 4-wide Multi Port LUT RAM
--         Versal Prime series
-- Xilinx HDL Language Template, version 2021.2

RAM64M_inst : RAM64M
generic map (
   INIT_A => X"0000000000000000",   -- Initial contents of A port
   INIT_B => X"0000000000000000",   -- Initial contents of B port
   INIT_C => X"0000000000000000",   -- Initial contents of C port
   INIT_D => X"0000000000000000",    -- Initial contents of D port
   IS_WCLK_INVERTED => '0') -- Specifies active high/low WCLK
port map (
   DOA => DOA, -- Read port A 1-bit output
   DOB => DOB, -- Read port B 1-bit output
   DOC => DOC, -- Read port C 1-bit output
   DOD => DOD, -- Read/Write port D 1-bit output
   ADDRA => ADDRA,   -- Read port A 6-bit address input
   ADDRB => ADDRB,   -- Read port B 6-bit address input
   ADDRC => ADDRC,   -- Read port C 6-bit address input
   ADDRD => ADDRD,   -- Read/Write port D 6-bit address input
   DIA => DIA, -- RAM 1-bit data write input addressed by ADDRD,
               -- read addressed by ADDRA
   DIB => DIB, -- RAM 1-bit data write input addressed by ADDRD,
               -- read addressed by ADDRB
   DIC => DIC, -- RAM 1-bit data write input addressed by ADDRD,
               -- read addressed by ADDRC
   DID => DID, -- RAM 1-bit data write input addressed by ADDRD,
               -- read addressed by ADDRD
   WCLK => WCLK,  -- Write clock input
   WE => WE       -- Write enable input
);
-- End of RAM64M_inst instantiation

Verilog Instantiation Template


// RAM64M: 64-deep by 4-wide Multi Port LUT RAM (Mapped to four LUT6s)
//         Versal Prime series
// Xilinx HDL Language Template, version 2021.2

RAM64M #(
   .INIT_A(64'h0000000000000000), // Initial contents of A Port
   .INIT_B(64'h0000000000000000), // Initial contents of B Port
   .INIT_C(64'h0000000000000000), // Initial contents of C Port
   .INIT_D(64'h0000000000000000), // Initial contents of D Port
   .IS_WCLK_INVERTED(1'b0)        // Specifies active high/low WCLK
) RAM64M_inst (
   .DOA(DOA),     // Read port A 1-bit output
   .DOB(DOB),     // Read port B 1-bit output
   .DOC(DOC),     // Read port C 1-bit output
   .DOD(DOD),     // Read/write port D 1-bit output
   .DIA(DIA),     // RAM 1-bit data write input addressed by ADDRD,
                  //   read addressed by ADDRA
   .DIB(DIB),     // RAM 1-bit data write input addressed by ADDRD,
                  //   read addressed by ADDRB
   .DIC(DIC),     // RAM 1-bit data write input addressed by ADDRD,
                  //   read addressed by ADDRC
   .DID(DID),     // RAM 1-bit data write input addressed by ADDRD,
                  //   read addressed by ADDRD
   .ADDRA(ADDRA), // Read port A 6-bit address input
   .ADDRB(ADDRB), // Read port B 6-bit address input
   .ADDRC(ADDRC), // Read port C 6-bit address input
   .ADDRD(ADDRD), // Read/write port D 6-bit address input
   .WE(WE),       // Write enable input
   .WCLK(WCLK)    // Write clock input
);

// End of RAM64M_inst instantiation

Related Information

  • Versal ACAP Configurable Logic Block Architecture Manual (AM005)