GTYE5_QUAD - 2021.2 English

Versal Architecture AI Core Series Libraries Guide (UG1353)

Document ID
UG1353
Release Date
2021-10-22
Version
2021.2 English

Primitive: Gigabit Transceiver for Versal devices

  • PRIMITIVE_GROUP: ADVANCED
  • PRIMITIVE_SUBGROUP: GT

Introduction

The Versal ACAP GTY transceiver provides the greatest performance and integration at 7 nm, including serial I/O bandwidth and logic capacity. As the industry's high-end FPGA at the 7 nm process node, this product family is ideal for applications including 400G networking, large-scale ASIC prototyping, and emulation.

Design Entry Method

Instantiation No
Inference No
IP and IP Integrator Catalog Recommended

Related Information

  • Versal ACAP GTY and GTYP Transceivers Architecture Manual (AM002)