This guide is part of the Vivado® Design Suite documentation collection and is intended for use during the RTL design process, with Versal architecture AI Core series.
This guide contains the following:
- Descriptions of each available parameterized macro
- A list of design primitives supported in this series, organized by functional categories
- Descriptions of each available primitive
About Design Elements
This version of the Libraries Guide describes the valid design elements for Versal architecture AI Core series parts, and includes examples of instantiation code for each element. Instantiation templates are also available within the Language Templates in the Vivado® Design Suite, and are supplied in a separate ZIP file, which you can find on www.xilinx.com linked to this file.
Design elements are divided into the following main categories:
Macros: These elements are in the Xilinx Parameterized Macro library in the tool, and are used to instantiate elements that are too complex to instantiate by just using the primitives. The synthesis tools will automatically expand the macros to their underlying primitives.Important: Unimacros from previous generation Xilinx FPGA architectures are not supported in the Versal portfolio and have been replaced by Xilinx Parameterized Macros.
Primitives: Xilinx components that are native to the architecture you are targeting.
Design Entry Methods
For each design element in this guide, Xilinx evaluates the options for using the design element, and recommends what we believe is the best solution for you. The options are:
- Instantiation: This component can be instantiated directly into the design. This method is useful if you want to control the exact use, implementation, or placement of the individual blocks.
- Inference: This component can be inferred by most supported synthesis tools. You should use this method if you want to have complete flexibility and portability of the code to multiple architectures. Inference also gives the tools the ability to optimize for performance, area, or power, as specified by the user to the synthesis tool.
- IP and IP Integrator Catalog: This component can be instantiated from the IP Catalog. The IP Catalog maintains a library of IP Cores assembled from multiple primitives to form more complex functions, as well as interfaces to help in instantiation of the more complex primitives. References here to the IP Catalog generally refer to the latter, where you use the IP catalog to assist in the use and integration of certain primitives into your design.