MBUFGCTRL - 2021.2 English

Versal Architecture AI Core Series Libraries Guide (UG1353)

Document ID
UG1353
Release Date
2021-10-22
Version
2021.2 English

Primitive: Multi-Output Global Clock Control Buffer

  • PRIMITIVE_GROUP: CLOCK
  • PRIMITIVE_SUBGROUP: MUX

Introduction

This design element is a Multi-Output Global Clock Control Buffer. The MBUFGCTRL primitive is designed as a synchronous/asynchronous "glitch-free multiplexer" with two clock inputs and multiple outputs. If clock multiplexing is not necessary, you should use the MBUFGCE component. The multiple clock outputs are generated close to the leaf clock pins instead of at the Clock Management Tile, which reduces clock pessimism on synchronous clock domain crossing paths. The output clocks are generated based on the MODE attribute.

Port Descriptions

Port Direction Width Function
CE0 Input 1 Clock enable input for the I0 clock input. A setup/hold time must be guaranteed when you are using the CE0 pin to enable this input. Failure to meet this requirement could result in a clock glitch.
CE1 Input 1 Clock enable input for the I1 clock input. A setup/hold time must be guaranteed when you are using the CE1 pin to enable this input. Failure to meet this requirement could result in a clock glitch.
CLRB_LEAF Input 1 Active low clear of BUFDIV_LEAF
IGNORE0 Input 1 Clock ignore input for I0 input. Asserting the IGNORE pin prevents the MBUFGCTRL from detecting the conditions for switching between two clock inputs. In other words, asserting IGNORE causes the MUX to switch the inputs at the instant the select pin changes. IGNORE0 causes the output to switch away from the I0 input immediately when the select pin changes, while IGNORE1 causes the output to switch away from the I1 input immediately when the select pin changes.
IGNORE1 Input 1 Clock ignore input for I1 input. Asserting the IGNORE pin prevents the BUFGCTRL from detecting the conditions for switching between two clock inputs. In other words, asserting IGNORE causes the MUX to switch the inputs at the instant the select pin changes. IGNORE0 causes the output to switch away from the I0 input immediately when the select pin changes, while IGNORE1 causes the output to switch away from the I1 input immediately when the select pin changes.
I0 Input 1 Primary clock input into the MBUFGCTRL enabled by the CE0 input and selected by the S0 input.
I1 Input 1 Secondary clock input into the MBUFGCTRL enabled by the CE1 input and selected by the S1 input.
O1 Output 1
  • I in PERFORMANCE MODE
  • I*2 in POWER MODE
O2 Output 1
  • I/2 in PERFORMANCE MODE
  • I in POWER MODE
O3 Output 1
  • I/4 in PERFORMANCE MODE
  • I/2 in POWER MODE
O4 Output 1
  • I/8 in PERFORMANCE MODE
  • I/4 in POWER MODE
S0 Input 1 Clock select input for I0. The S pins represent the clock select pin for each clock input. When using the S pin as input select, there is a setup/hold time requirement. Unlike CE pins, failure to meet this requirement will not result in a clock glitch. However, it can cause the output clock to appear one clock cycle later.
S1 Input 1 Clock select input for I1. The S pins represent the clock select pin for each clock input. When using the S pin as input select, there is a setup/hold time requirement. Unlike CE pins, failure to meet this requirement will not result in a clock glitch. However, it can cause the output clock to appear one clock cycle later.

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog Recommended

Available Attributes

Attribute Type Allowed Values Default Description
CE_TYPE_CE0 STRING "SYNC", "HARDSYNC" "SYNC" Sets the CE0 clock enable behavior where SYNC allows for glitchless transition while ASYNC allows immediate transition. The SYNC setting times the CE pin in the Vivado tools while the ASYNC setting ignores the timing arc. HARD_SYNC turns on an internal 3-stage synchronizer for maximum performance. However, that results in a latency of either three or four clock cycles.
CE_TYPE_CE1 STRING "SYNC", "HARDSYNC" "SYNC" Sets the CE1 clock enable behavior where SYNC allows for glitchless transition while ASYNC allows immediate transition. The SYNC setting times the CE pin in the Vivado tools while the ASYNC setting ignores the timing arc. HARD_SYNC turns on an internal 3-stage synchronizer for maximum performance. However, that results in a latency of either three or four clock cycles.
INIT_OUT DECIMAL 0, 1 0 Initializes the MBUFGCTRL output to the specified value after configuration. Sets the positive or negative edge behavior. Sets the output level when changing clock selection.
IS_CE0_INVERTED BINARY 1'b0 to 1'b1 1'b0 Programmable inversion on CE0
IS_CE1_INVERTED BINARY 1'b0 to 1'b1 1'b0 Programmable inversion on CE1
IS_IGNORE0_INVERTED BINARY 1'b0 to 1'b1 1'b0 Programmable inversion on IGNORE0
IS_IGNORE1_INVERTED BINARY 1'b0 to 1'b1 1'b0 Programmable inversion on IGNORE1
IS_I0_INVERTED BINARY 1'b0 to 1'b1 1'b0 Programmable inversion on I0
IS_I1_INVERTED BINARY 1'b0 to 1'b1 1'b0 Programmable inversion on I1
IS_S0_INVERTED BINARY 1'b0 to 1'b1 1'b0 Programmable inversion on S0
IS_S1_INVERTED BINARY 1'b0 to 1'b1 1'b0 Programmable inversion on S1
MODE STRING "PERFORMANCE", "POWER" "PERFORMANCE"

Sets the mode of operation that determines the output clock generation.

For PERFORMANCE MODE, the outputs are generated as follows:
  • O1 = I
  • O2 = I/2
  • O3 = I/4
  • O4 = I/8
For POWER MODE, the outputs are generated as follows:
  • O1 = I*2
  • O2 = I
  • O3 = I/2
  • O4 = I/4
PRESELECT_I0 STRING "FALSE", "TRUE" "FALSE" If TRUE, MBUFGCTRL output uses I0 input after configuration.
PRESELECT_I1 STRING "FALSE", "TRUE" "FALSE" If TRUE, MBUFGCTRL output uses I1 input after configuration.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- MBUFGCTRL: Multi-Output Global Clock Control Buffer
--            Versal AI Core series
-- Xilinx HDL Language Template, version 2021.2

MBUFGCTRL_inst : MBUFGCTRL
generic map (
   CE_TYPE_CE0 => "SYNC",      -- HARDSYNC, SYNC
   CE_TYPE_CE1 => "SYNC",      -- HARDSYNC, SYNC
   INIT_OUT => 0,              -- Initial value of MBUFGCTRL output, (0-1)
   IS_CE0_INVERTED => '0',     -- Programmable inversion on CE0
   IS_CE1_INVERTED => '0',     -- Programmable inversion on CE1
   IS_I0_INVERTED => '0',      -- Programmable inversion on I0
   IS_I1_INVERTED => '0',      -- Programmable inversion on I1
   IS_IGNORE0_INVERTED => '0', -- Programmable inversion on IGNORE0
   IS_IGNORE1_INVERTED => '0', -- Programmable inversion on IGNORE1
   IS_S0_INVERTED => '0',      -- Programmable inversion on S0
   IS_S1_INVERTED => '0',      -- Programmable inversion on S1
   MODE => "PERFORMANCE",      -- PERFORMANCE, POWER
   PRESELECT_I0 => "FALSE",    -- MBUFGCTRL output uses I0 input, (FALSE, TRUE)
   PRESELECT_I1 => "FALSE"     -- MBUFGCTRL output uses I1 input, (FALSE, TRUE)
)
port map (
   O1 => O1,               -- 1-bit output: Buffer
   O2 => O2,               -- 1-bit output:  I/2 in PERFORMANCE MODE I in POWER MODE
   O3 => O3,               -- 1-bit output:  I/4 in PERFORMANCE MODE I/2 in POWER MODE
   O4 => O4,               -- 1-bit output:  I/8 in PERFORMANCE MODE I/4 in POWER MODE
   CE0 => CE0,             -- 1-bit input: Clock enable input for I0
   CE1 => CE1,             -- 1-bit input: Clock enable input for I1
   CLRB_LEAF => CLRB_LEAF, -- 1-bit input: Active low clear
   I0 => I0,               -- 1-bit input: Primary clock
   I1 => I1,               -- 1-bit input: Secondary clock
   IGNORE0 => IGNORE0,     -- 1-bit input: Clock ignore input for I0
   IGNORE1 => IGNORE1,     -- 1-bit input: Clock ignore input for I1
   S0 => S0,               -- 1-bit input: Clock select for I0
   S1 => S1                -- 1-bit input: Clock select for I1
);

-- End of MBUFGCTRL_inst instantiation

Verilog Instantiation Template


// MBUFGCTRL: Multi-Output Global Clock Control Buffer
//            Versal AI Core series
// Xilinx HDL Language Template, version 2021.2

MBUFGCTRL #(
   .CE_TYPE_CE0("SYNC"),       // HARDSYNC, SYNC
   .CE_TYPE_CE1("SYNC"),       // HARDSYNC, SYNC
   .INIT_OUT(0),               // Initial value of MBUFGCTRL output, (0-1)
   .IS_CE0_INVERTED(1'b0),     // Programmable inversion on CE0
   .IS_CE1_INVERTED(1'b0),     // Programmable inversion on CE1
   .IS_I0_INVERTED(1'b0),      // Programmable inversion on I0
   .IS_I1_INVERTED(1'b0),      // Programmable inversion on I1
   .IS_IGNORE0_INVERTED(1'b0), // Programmable inversion on IGNORE0
   .IS_IGNORE1_INVERTED(1'b0), // Programmable inversion on IGNORE1
   .IS_S0_INVERTED(1'b0),      // Programmable inversion on S0
   .IS_S1_INVERTED(1'b0),      // Programmable inversion on S1
   .MODE("PERFORMANCE"),       // PERFORMANCE, POWER
   .PRESELECT_I0("FALSE"),     // MBUFGCTRL output uses I0 input, (FALSE, TRUE)
   .PRESELECT_I1("FALSE")      // MBUFGCTRL output uses I1 input, (FALSE, TRUE)
)
MBUFGCTRL_inst (
   .O1(O1),               // 1-bit output: Buffer
   .O2(O2),               // 1-bit output:  I/2 in PERFORMANCE MODE I in POWER MODE
   .O3(O3),               // 1-bit output:  I/4 in PERFORMANCE MODE I/2 in POWER MODE
   .O4(O4),               // 1-bit output:  I/8 in PERFORMANCE MODE I/4 in POWER MODE
   .CE0(CE0),             // 1-bit input: Clock enable input for I0
   .CE1(CE1),             // 1-bit input: Clock enable input for I1
   .CLRB_LEAF(CLRB_LEAF), // 1-bit input: Active low clear
   .I0(I0),               // 1-bit input: Primary clock
   .I1(I1),               // 1-bit input: Secondary clock
   .IGNORE0(IGNORE0),     // 1-bit input: Clock ignore input for I0
   .IGNORE1(IGNORE1),     // 1-bit input: Clock ignore input for I1
   .S0(S0),               // 1-bit input: Clock select for I0
   .S1(S1)                // 1-bit input: Clock select for I1
);

// End of MBUFGCTRL_inst instantiation

Related Information

  • Versal ACAP Clocking Resources Architecture Manual (AM003)