ODELAYE5 - 2021.2 English

Versal Architecture AI Core Series Libraries Guide (UG1353)

Document ID
UG1353
Release Date
2021-10-22
Version
2021.2 English

Primitive: Output Delay Element

  • PRIMITIVE_GROUP: I/O
  • PRIMITIVE_SUBGROUP: DELAY

Introduction

The ODELAYE5 is an uncalibrated output delay element that can be connected to an output register/ODDR or driven directly into device logic. The ODELAYE5 is a 32-tap uncalibrated delay element that allows for outgoing signals to be delayed on an individual basis. Refer to the device Data Sheet for delay values.

Port Descriptions

Port Direction Width Function
CASC_IN Input 1 Cascade delay from IDELAYE5 output cascade.
CE Input 1 Active-High enable increment/decrement input.
CLK Input 1 Clock Input
CNTVALUEIN<4:0> Input 5 Counter value from device logic for dynamically loadable tap value input.
CNTVALUEOUT<4:0> Output 5 Counter value to device logic for reporting tap value of the delay element.
DATAOUT Output 1 Delayed data from ODATAIN or CASC_IN.
INC Input 1 Increment/decrement tap delay input.
LOAD Input 1 Load the value of CNTVALUEIN.
ODATAIN Input 1 Data input for ODELAYE5 from ODDR or programmable logic.
RST Input 1 Asynchronous Reset, active level based on IS_RST_INVERTED.
TDATAIN Input 1 Tristate input for ODELAYE5 from ODDR or programmable logic.
TDATAOUT Output 1 Delayed tristate from TDATAIN.

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog No

Available Attributes

Attribute Type Allowed Values Default Description
CASCADE STRING "FALSE", "TRUE" "FALSE" The CASCADE attribute is set to TRUE when the ODELAYE5 is used to cascade the IDELAYE5.
IS_CLK_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether the CLK pin is active-High or active-Low.
IS_RST_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether the RST pin is active-High or active-Low.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- ODELAYE5: Output Delay Element
--           Versal AI Core series
-- Xilinx HDL Language Template, version 2021.2

ODELAYE5_inst : ODELAYE5
generic map (
   CASCADE => "FALSE",     -- Cascade setting (FALSE, TRUE)
   IS_CLK_INVERTED => '0', -- Optional inversion for CLK
   IS_RST_INVERTED => '0'  -- Optional inversion for RST
)
port map (
   CNTVALUEOUT => CNTVALUEOUT, -- 5-bit output: Counter value output
   DATAOUT => DATAOUT,         -- 1-bit output: Delayed data
   TDATAOUT => TDATAOUT,       -- 1-bit output: Delayed tristate
   CASC_IN => CASC_IN,         -- 1-bit input: Cascade delay from IDELAYE5 output cascade
   CE => CE,                   -- 1-bit input: Active-High enable increment/decrement input
   CLK => CLK,                 -- 1-bit input: Clock Input
   CNTVALUEIN => CNTVALUEIN,   -- 5-bit input: Counter value input
   INC => INC,                 -- 1-bit input: Increment / Decrement tap delay input
   LOAD => LOAD,               -- 1-bit input: Load CNTVALUEIN
   ODATAIN => ODATAIN,         -- 1-bit input: Data input
   RST => RST,                 -- 1-bit input: Asynchronous Reset
   TDATAIN => TDATAIN          -- 1-bit input: Tristate input
);

-- End of ODELAYE5_inst instantiation

Verilog Instantiation Template


// ODELAYE5: Output Delay Element
//           Versal AI Core series
// Xilinx HDL Language Template, version 2021.2

ODELAYE5 #(
   .CASCADE("FALSE"),      // Cascade setting (FALSE, TRUE)
   .IS_CLK_INVERTED(1'b0), // Optional inversion for CLK
   .IS_RST_INVERTED(1'b0)  // Optional inversion for RST
)
ODELAYE5_inst (
   .CNTVALUEOUT(CNTVALUEOUT), // 5-bit output: Counter value output
   .DATAOUT(DATAOUT),         // 1-bit output: Delayed data
   .TDATAOUT(TDATAOUT),       // 1-bit output: Delayed tristate
   .CASC_IN(CASC_IN),         // 1-bit input: Cascade delay from IDELAYE5 output cascade
   .CE(CE),                   // 1-bit input: Active-High enable increment/decrement input
   .CLK(CLK),                 // 1-bit input: Clock Input
   .CNTVALUEIN(CNTVALUEIN),   // 5-bit input: Counter value input
   .INC(INC),                 // 1-bit input: Increment / Decrement tap delay input
   .LOAD(LOAD),               // 1-bit input: Load CNTVALUEIN
   .ODATAIN(ODATAIN),         // 1-bit input: Data input
   .RST(RST),                 // 1-bit input: Asynchronous Reset
   .TDATAIN(TDATAIN)          // 1-bit input: Tristate input
);

// End of ODELAYE5_inst instantiation

Related Information

  • Versal ACAP SelectIO Resources Architecture Manual (AM010)