RAMB18E5 - 2021.2 English

Versal Architecture AI Core Series Libraries Guide (UG1353)

Document ID
UG1353
Release Date
2021-10-22
Version
2021.2 English

Primitive: 18K-bit Configurable Synchronous Block RAM

  • PRIMITIVE_GROUP: BLOCKRAM
  • PRIMITIVE_SUBGROUP: BRAM

Introduction

The RAMB18E5 allows access to the block RAM memory in the 18 Kb configuration. This element can be configured and used as a 9-bit wide by 2K deep to an 18-bit wide by 1K deep true dual port RAM. This element can also be configured as a 36-bit wide by 512 deep simple dual port RAM. Both read and write operations are fully synchronous to the supplied clock(s) to the component. However, the READ and WRITE ports can operate fully independent and asynchronous to each other, accessing the same memory array. When configured in the wider data width modes, byte-enable write operations are possible, and an optional output register can be used to reduce the clock-to-out times of the RAM. This RAM also features a cascade capability, which lets you chain multiple RAMB18E5 components to form deeper and more power efficient memory configurations if desired.

Port Descriptions

Port Direction Width Function
Cascade Signals: Signals used when cascading more than one RAMB18E5 components.
CASDINA<15:0> Input 16 Port A cascade input data.
CASDINB<15:0> Input 16 Port B cascade input data.
CASDINPA<1:0> Input 2 Port A cascade input parity data.
CASDINPB<1:0> Input 2 Port B cascade input parity data.
CASDOMUXA Input 1 Port A mux control input to select between output data from BRAM (registered or unregistered) or CASCADE data input (CASDINA).
CASDOMUXB Input 1 Port B mux control input to select between output data from BRAM (registered or unregistered) or CASCADE data input (CASDINB).
CASDOMUXEN_A Input 1 Port A unregistered output data register enable.
CASDOMUXEN_B Input 1 Port B unregistered output data register enable.
CASDOUTA<15:0> Output 16 Port A cascade output data.
CASDOUTB<15:0> Output 16 Port B cascade output data.
CASDOUTPA<1:0> Output 2 Port A cascade output parity data.
CASDOUTPB<1:0> Output 2 Port B cascade output parity data.
CASOREGIMUXA Input 1 Port A mux control input to select between output data from BRAM or CASCADE data input (CASDINA).
CASOREGIMUXB Input 1 Port B mux control input to select between output data from BRAM or CASCADE data input (CASDINB).
CASOREGIMUXEN_A Input 1 Port A registered output data register enable.
CASOREGIMUXEN_B Input 1 Port B registered output data register enable.
Port A Address/Control Signals: Port A address and control (clock, reset, enables, etc.) signals.
ADDRARDADDR<10:0> Input 11 Port A address input bus/Read address input bus.
ARST_A Input 1 Asynchronous reset that resets the output register for Port A to all zeros.
CLKARDCLK Input 1 Port A clock input/Read clock input.
ENARDEN Input 1 Port A RAM enable/Read enable. For best power characteristics of this component, it is suggested to drive this pin Low when ever a new read or write operation is not necessary on Port A. Significant power savings can be seen when this port is driven Low.
REGCEAREGCE Input 1 Port A output register clock enable input/Output register clock enable input (valid only when DOA_REG=1).
RSTRAMARSTRAM Input 1 Synchronous data latch set/reset to value indicated by SRVAL_A. RSTRAMARSTRAM sets/resets the BRAM data output latch when DO_REG=0 or 1. If DO_REG=1 there is a cycle of latency between the internal data latch node that is reset by RSTRAMARSTRAM and the DO output of the BRAM. This signal resets port A RAM output when READ_WIDTH≤18 and the entire RAM output when READ_WIDTH=36.
RSTREGARSTREG Input 1 Synchronous output register set/reset to value indicated by SRVAL_A. RSTREGARSTREG sets/resets the output register when DO_REG=1. RSTREG_PRIORITY_A determines if this signal gets priority over REGCEAREGCE. This signal resets port A output when READ_WIDTH≤18 and the entire RAM output when READ_WIDTH=36.
WEA<1:0> Input 2 Port A byte-wide write enable. In the case that port A is write-only and byte-write operation is not necessary, it is suggested to connect all bits high and control write operation with the ENARDEN port. Doing this improves power consumption of the block RAM. In wide 36-bit mode or port A is read-only or not used, tie all bits Low. In other modes, the connections are dependent on WRITE_WIDTH_A setting. See the Versal ACAP Memory Resources Architecture Manual (AM007) for WEA mapping for different port widths.
Port A Data: Port A data signals.
DINADIN<15:0> Input 16 Port A data input bus. When WRITE_WIDTH=36, DINADIN is the logical DI<15:0>.
DINPADINP<1:0> Input 2 Port A parity data input bus/Data parity input bus addressed by WRADDR. When WRITE_WIDTH=36, DINPADINP is the logical DIP<1:0>.
DOUTADOUT<15:0> Output 16 Port A data output bus. When READ_WIDTH=36, DOUTADOUT is the logical DO<15:0>.
DOUTPADOUTP<1:0> Output 2 Port A parity data output bus. When READ_WIDTH=36, DOUTPADOUT is the logical DOP<1:0>.
Port B Address/Control Signals: Port B address and control (clock, reset, enables, etc.).
ADDRBWRADDR<10:0> Input 11 Port B address input bus/Write address input bus.
ARST_B Input 1 Asynchronous reset that resets the output register for Port B to all zeros.
CLKBWRCLK Input 1 Port B clock input/Write clock input.
ENBWREN Input 1 Port B RAM enable/Write enable. For best power characteristics of this component, it is suggested to drive this pin Low when ever a new read or write operation is not necessary on Port B. Significant power savings can be seen when this port is driven Low.
REGCEB Input 1 Port B output register clock enable (valid only when DOB_REG=1 and READ_WIDTH≤18).
RSTRAMB Input 1 Synchronous data latch set/reset to value indicated by SRVAL_B. RSTRAMB sets/resets the BRAM data output latch when DO_REG=0 or 1. If DO_REG=1 there is a cycle of latency between the internal data latch node that is reset by RSTRAMB and the DO output of the BRAM. Not used when READ_WIDTH=36.
RSTREGB Input 1 Synchronous output register set/reset to value indicated by SRVAL_B. RSTREGB sets/resets the output register when DO_REG=1. RSTREG_PRIORITY_B determines if this signal gets priority over REGCEB. Not used when READ_WIDTH=36.
SLEEP Input 1 Dynamic shut down power saving. If SLEEP is High, the block is in power saving mode. If SLEEP_ASYNC=FALSE, synchronous to RDCLK, otherwise, asynchronous input. Using this pin can save additional power if the RAM is not accessed for sustained amounts of time.
WEBWE<3:0> Input 4 Port B byte-wide write enable/Write enable. In the case that port B is write-only and byte-write operation is not necessary, it is suggested to connect all bits high and control write operation with the ENBWREN port. Doing this improves power consumption of the block RAM. In the case that port B is read-only or not used, tie all bits Low. In other modes, the connections are dependent on WRITE_WIDTH_B setting. See the Versal ACAP Memory Resources Architecture Manual (AM007) for WEBWE mapping for different port widths.
Port B Data: Port B data signals.
DINBDIN<15:0> Input 16 Port B data input bus. When WRITE_WIDTH=36, DINBDIN is the logical DI<31:16>.
DINPBDINP<1:0> Input 2 Port B parity data input bus/Data parity input bus addressed by WRADDR. When WRITE_WIDTH=36, DINPBDINP is the logical DIP<3:2>.
DOUTBDOUT<15:0> Output 16 Port B data output bus. When READ_WIDTH=36, DOUTBDOUT is the logical DO<31:16>.
DOUTPBDOUTP<1:0> Output 2 Port B parity data output bus. When READ_WIDTH=36, DOUTPBDOUTP is the logical DOP<3:2>.

Design Entry Method

Instantiation Yes
Inference Recommended
IP and IP Integrator Catalog Yes

Available Attributes

Attribute Type Allowed Values Default Description
CASCADE_ORDER_A, CASCADE_ORDER_B: Specifies the order of the cascaded BRAM. FIRST BRAM is the bottom in cascade, LAST one is on the top of the cascade, and MIDDLE is the BRAM in between bottom and top.
CASCADE_ORDER_A STRING "NONE", "FIRST", "LAST", "MIDDLE" "NONE" Specifies the cascade order for Port A.
CASCADE_ORDER_B STRING "NONE", "FIRST", "LAST", "MIDDLE" "NONE" Specifies the cascade order for Port B.
CLOCK_DOMAINS: Used for Simulation to model the address collision case as well as to enable lower power operation in common clock mode.
  • "COMMON":Common Clock/Single Clock.
  • "INDEPENDENT": Independent Clock/Dual Clock.
CLOCK_DOMAINS STRING "INDEPENDENT", "COMMON" "INDEPENDENT" Used for Simulation to model the address collision case as well as to enable lower power operation in common clock mode.
  • "COMMON":Common Clock/Single Clock.
  • "INDEPENDENT": Independent Clock/Dual Clock.
Collision check: Modifies the simulation behavior so that if a memory collision occurs
  • "ALL": Warning produced and affected outputs/memory go unknown (X)
  • "WARNING_ONLY": Warning produced and affected outputs/memory retain last value.
  • "GENERATE_X_ONLY": No warning and affected outputs/memory go unknown (X).
  • "NONE": No warning and affected outputs/memory retain last value.
Note: Use this setting carefully. Setting it to a value other than "ALL" can mask design problems during simulation.
SIM_COLLISION_CHECK STRING "ALL", "GENERATE_X_ONLY", "NONE", "WARNING_ONLY" "ALL" Modifies the simulation behavior so that if a memory collision occurs
  • "ALL": Warning produced and affected outputs/memory go unknown (X)
  • "WARNING_ONLY": Warning produced and affected outputs/memory retain last value.
  • "GENERATE_X_ONLY": No warning and affected outputs/memory go unknown (X).
  • "NONE": No warning and affected outputs/memory retain last value.
Note: Use this setting carefully. Setting it to a value other than "ALL" can mask design problems during simulation.
DOA_REG, DOB_REG: A value of 1 enables the output registers to the RAM enabling higher performance clock-to-out from the RAM at the expense of an added clock cycle of read latency. A value of 0 allows a read in one clock cycle but will result in slower clock-to-out timing.
DOA_REG DECIMAL 1, 0 1 A value of 1 enables the output registers to the RAM enabling higher performance clock-to-out from the RAM at the expense of an added clock cycle of read latency. A value of 0 allows a read in one clock cycle but will result in slower clock-to-out timing.
DOB_REG DECIMAL 1, 0 1 A value of 1 enables the output registers to the RAM enabling higher performance clock-to-out from the RAM at the expense of an added clock cycle of read latency. A value of 0 allows a read in one clock cycle but will result in slower clock-to-out timing.
INIT_00 to INIT_3F: Specifies the initial contents of the 16 Kb data memory array.
INIT_00 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_0A HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_0B HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_0C HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_0D HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_0E HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_0F HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_01 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_1A HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_1B HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_1C HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_1D HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_1E HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_1F HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_02 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_2A HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_2B HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_2C HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_2D HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_2E HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_2F HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_03 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_3A HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_3B HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_3C HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_3D HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_3E HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_3F HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_04 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_05 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_06 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_07 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_08 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_09 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_10 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_11 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_12 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_13 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_14 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_15 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_16 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_17 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_18 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_19 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_20 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_21 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_22 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_23 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_24 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_25 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_26 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_27 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_28 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_29 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_30 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_31 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_32 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_33 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_34 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_35 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_36 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_37 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_38 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
INIT_39 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 16 Kb data memory array.
Initialization File: File name of file used to specify initial RAM contents.
INIT_FILE STRING String "NONE" File name of file used to specify initial RAM contents.
INITP_00 to INITP_07: Specifies the initial contents of the 2 Kb parity data memory array.
INITP_00 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 2 Kb parity data memory array.
INITP_01 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 2 Kb parity data memory array.
INITP_02 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 2 Kb parity data memory array.
INITP_03 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 2 Kb parity data memory array.
INITP_04 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 2 Kb parity data memory array.
INITP_05 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 2 Kb parity data memory array.
INITP_06 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 2 Kb parity data memory array.
INITP_07 HEX Any 256-bit HEX value All zeroes Specifies the initial contents of the 2 Kb parity data memory array.
PartialReconfig: Enables skipping of content initialization after partial reconfiguration to maintain previous memory content.
PR_SAVE_DATA STRING "FALSE", "TRUE" "FALSE" Enables skipping of content initialization after partial reconfiguration to maintain previous memory content.
Programmable Inversion Attributes: Specifies whether or not to use the optional inversions on specific pins of this component to change the active polarity of the pin function. When set to 1 on a clock pin (WRCLK or RDCLK), this components clocks on the negative edge. When set to 1 on other pins, it changes the function to behave active-Low rather than active-High. For pins that are buses, the bit-width of this attribute should match that of the bit-width of the associated pins and a binary value indicates which inverters to use and which to bypass. If an external inverter is specified on one of these associated pins, the Vivado Design Suite will automatically set this attribute during the opt_design stage, so that additional logic is not necessary for changing the input polarity.
IS_ARST_A_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the ARST_A pin.
IS_ARST_B_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the ARST_B pin.
IS_CLKARDCLK_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the CLKARDCLK pin.
IS_CLKBWRCLK_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the CLKBWRCLK pin.
IS_ENARDEN_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the ENARDEN pin.
IS_ENBWREN_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the ENBWREN pin.
IS_RSTRAMARSTRAM_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the RSTRAMARSTRAM pin.
IS_RSTRAMB_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the RSTRAMB pin.
IS_RSTREGARSTREG_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the RSTREGARSTREG pin.
IS_RSTREGB_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the RSTREGB pin.
READ_WIDTH_A/B, WRITE_WIDTH_A/B: Specifies the desired data width for a read/write on port A/B, including parity bits. This value must be 0 if the port is not used. Otherwise, it should be set to the desired port width.
READ_WIDTH_A DECIMAL 0, 9, 18, 36 0 Specifies the desired data width for a read/write on port A/B, including parity bits. This value must be 0 if the port is not used. Otherwise, it should be set to the desired port width.
READ_WIDTH_B DECIMAL 0, 9, 18 0 Specifies the desired data width for a read/write on port A/B, including parity bits. This value must be 0 if the port is not used. Otherwise, it should be set to the desired port width.
WRITE_WIDTH_A DECIMAL 0, 9, 18 0 Specifies the desired data width for a read/write on port A/B, including parity bits. This value must be 0 if the port is not used. Otherwise, it should be set to the desired port width.
WRITE_WIDTH_B DECIMAL 0, 9, 18, 36 0 Specifies the desired data width for a read/write on port A/B, including parity bits. This value must be 0 if the port is not used. Otherwise, it should be set to the desired port width.
RST_MODE_A, RST_MODE_B: Specifies if the user reset signal is synchronous (SYNC) or asynchronous (ASYNC). The default value is SYNC, which means the RSTRAM or RSTREG (if output registers are used) to a specified SRVAL. If this attribute is set to ASYNC, the ARST_A/B resets all pipe stages of the block RAM to 0. The value of RSTRAM and RSTREG inputs are ignored and not propagated to the block RAM circuit. The SRVAL setting is also ignored.
RST_MODE_A STRING "SYNC", "ASYNC" "SYNC" Specifies if the user reset signal is synchronous (SYNC) or asynchronous (ASYNC). The default value is SYNC, which means the RSTRAM or RSTREG (if output registers are used) to a specified SRVAL. If this attribute is set to ASYNC, the ARST_A/B resets all pipe stages of the block RAM to 0. The value of RSTRAM and RSTREG inputs are ignored and not propagated to the block RAM circuit. The SRVAL setting is also ignored.
RST_MODE_B STRING "SYNC", "ASYNC" "SYNC" Specifies if the user reset signal is synchronous (SYNC) or asynchronous (ASYNC). The default value is SYNC, which means the RSTRAM or RSTREG (if output registers are used) to a specified SRVAL. If this attribute is set to ASYNC, the ARST_A/B resets all pipe stages of the block RAM to 0. The value of RSTRAM and RSTREG inputs are ignored and not propagated to the block RAM circuit. The SRVAL setting is also ignored.
RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Selects register priority for RSTREG or REGCE.
RSTREG_PRIORITY_A STRING "RSTREG", "REGCE" "RSTREG" Selects register priority for RSTREG or REGCE.
RSTREG_PRIORITY_B STRING "RSTREG", "REGCE" "RSTREG" Selects register priority for RSTREG or REGCE.
Sleep Async: Specifies whether the SLEEP pin is synchronous to the CLKARDCLK pin ("FALSE") or treated as an asynchronous pin.
SLEEP_ASYNC STRING "FALSE", "TRUE" "FALSE" Specifies whether the SLEEP pin is synchronous to the CLKARDCLK pin ("FALSE") or treated as an asynchronous pin.
SRVAL_A, SRVAL_B: Specifies the output value of the RAM upon assertion of the synchronous reset (RST/RSTREG) signal.
SRVAL_A HEX 18'h00000 to 18'h3ffff All zeroes Specifies the output value for port A.
SRVAL_B HEX 18'h00000 to 18'h3ffff All zeroes Specifies the output value for port B.
WriteMode: Specifies output behavior of the port being written to.
  • "WRITE_FIRST": Written value appears on output port of the RAM.
  • "READ_FIRST": Previous RAM contents for that memory location appear on the output port. When the same clock is used for both ports, this mode also allows address collision avoidance when reading and writing to the same address from different ports.
  • "NO_CHANGE": Previous value on the output port remains the same. This is the lowest power mode.
When using the RAM as a simple dual-port (one port is read-only and one is write-only) it is suggested to set the WRITE_MODEs to NO_CHANGE if using different clocks on both ports or if address collisions can be avoided. It is suggested to set this to READ_FIRST mode only if using the same clock on both ports and address collisions can not be avoided in the design. WRITE_FIRST mode is not suggested to be used for simple dual-port operation as it consumes additional power over NO_CHANGE mode with no functional difference.
WRITE_MODE_A STRING "NO_CHANGE", "READ_FIRST", "WRITE_FIRST" "NO_CHANGE" Specifies output behavior of the port being written to.
  • "WRITE_FIRST": Written value appears on output port of the RAM.
  • "READ_FIRST": Previous RAM contents for that memory location appear on the output port. When the same clock is used for both ports, this mode also allows address collision avoidance when reading and writing to the same address from different ports.
  • "NO_CHANGE": Previous value on the output port remains the same. This is the lowest power mode.
When using the RAM as a simple dual-port (one port is read-only and one is write-only) it is suggested to set the WRITE_MODEs to NO_CHANGE if using different clocks on both ports or if address collisions can be avoided. It is suggested to set this to READ_FIRST mode only if using the same clock on both ports and address collisions can not be avoided in the design. WRITE_FIRST mode is not suggested to be used for simple dual-port operation as it consumes additional power over NO_CHANGE mode with no functional difference.
WRITE_MODE_B STRING "NO_CHANGE", "READ_FIRST", "WRITE_FIRST" "NO_CHANGE" Specifies output behavior of the port being written to.
  • "WRITE_FIRST": Written value appears on output port of the RAM.
  • "READ_FIRST": Previous RAM contents for that memory location appear on the output port. When the same clock is used for both ports, this mode also allows address collision avoidance when reading and writing to the same address from different ports.
  • "NO_CHANGE": Previous value on the output port remains the same. This is the lowest power mode.
When using the RAM as a simple dual-port (one port is read-only and one is write-only) it is suggested to set the WRITE_MODEs to NO_CHANGE if using different clocks on both ports or if address collisions can be avoided. It is suggested to set this to READ_FIRST mode only if using the same clock on both ports and address collisions can not be avoided in the design. WRITE_FIRST mode is not suggested to be used for simple dual-port operation as it consumes additional power over NO_CHANGE mode with no functional difference.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- RAMB18E5: 18K-bit Configurable Synchronous Block RAM
--           Versal AI Core series
-- Xilinx HDL Language Template, version 2021.2

RAMB18E5_inst : RAMB18E5
generic map (
   -- CASCADE_ORDER_A, CASCADE_ORDER_B: "FIRST", "MIDDLE", "LAST", "NONE"
   CASCADE_ORDER_A => "NONE",
   CASCADE_ORDER_B => "NONE",
   -- CLOCK_DOMAINS: "COMMON", "INDEPENDENT"
   CLOCK_DOMAINS => "INDEPENDENT",
   -- Collision check: "ALL", "GENERATE_X_ONLY", "NONE", "WARNING_ONLY"
   SIM_COLLISION_CHECK => "ALL",
   -- DOA_REG, DOB_REG: Optional output register (0, 1)
   DOA_REG => 1,
   DOB_REG => 1,
   -- INITP_00 to INITP_07: Initial contents of parity memory array
   INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
   -- INIT_00 to INIT_3F: Initial contents of data memory array
   INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
   INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
   -- Initialization File: RAM initialization file
   INIT_FILE => "NONE",
   -- PartialReconfig: Skip initialization after partial reconfiguration
   PR_SAVE_DATA => "FALSE",
   -- Programmable Inversion Attributes: Specifies the use of the built-in programmable inversion
   IS_ARST_A_INVERTED => '0',
   IS_ARST_B_INVERTED => '0',
   IS_CLKARDCLK_INVERTED => '0',
   IS_CLKBWRCLK_INVERTED => '0',
   IS_ENARDEN_INVERTED => '0',
   IS_ENBWREN_INVERTED => '0',
   IS_RSTRAMARSTRAM_INVERTED => '0',
   IS_RSTRAMB_INVERTED => '0',
   IS_RSTREGARSTREG_INVERTED => '0',
   IS_RSTREGB_INVERTED => '0',
   -- READ_WIDTH_A/B, WRITE_WIDTH_A/B: Read/write width per port
   READ_WIDTH_A => 0,                                                               -- 0-9
   READ_WIDTH_B => 0,                                                               -- 0-9
   WRITE_WIDTH_A => 0,                                                              -- 0-9
   WRITE_WIDTH_B => 0,                                                              -- 0-9
   -- RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG", "REGCE")
   RSTREG_PRIORITY_A => "RSTREG",
   RSTREG_PRIORITY_B => "RSTREG",
   -- RST_MODE_A, RST_MODE_B: Set synchronous or asynchronous reset.
   RST_MODE_A => "SYNC",
   RST_MODE_B => "SYNC",
   -- SRVAL_A, SRVAL_B: Set/reset value for output
   SRVAL_A => X"00000",
   SRVAL_B => X"00000",
   -- Sleep Async: Sleep function asynchronous or synchronous ("TRUE", "FALSE")
   SLEEP_ASYNC => "FALSE",
   -- WriteMode: "WRITE_FIRST", "NO_CHANGE", "READ_FIRST"
   WRITE_MODE_A => "NO_CHANGE",
   WRITE_MODE_B => "NO_CHANGE"
)
port map (
   -- Cascade Signals outputs: Multi-BRAM cascade signals
   CASDOUTA => CASDOUTA,               -- 16-bit output: Port A cascade output data
   CASDOUTB => CASDOUTB,               -- 16-bit output: Port B cascade output data
   CASDOUTPA => CASDOUTPA,             -- 2-bit output: Port A cascade output parity data
   CASDOUTPB => CASDOUTPB,             -- 2-bit output: Port B cascade output parity data
   -- Port A Data outputs: Port A data
   DOUTADOUT => DOUTADOUT,             -- 16-bit output: Port A data/LSB data
   DOUTPADOUTP => DOUTPADOUTP,         -- 2-bit output: Port A parity/LSB parity
   -- Port B Data outputs: Port B data
   DOUTBDOUT => DOUTBDOUT,             -- 16-bit output: Port B data/MSB data
   DOUTPBDOUTP => DOUTPBDOUTP,         -- 2-bit output: Port B parity/MSB parity
   -- Cascade Signals inputs: Multi-BRAM cascade signals
   CASDINA => CASDINA,                 -- 16-bit input: Port A cascade input data
   CASDINB => CASDINB,                 -- 16-bit input: Port B cascade input data
   CASDINPA => CASDINPA,               -- 2-bit input: Port A cascade input parity data
   CASDINPB => CASDINPB,               -- 2-bit input: Port B cascade input parity data
   CASDOMUXA => CASDOMUXA,             -- 1-bit input: Port A unregistered data (0=BRAM data, 1=CASDINA)
   CASDOMUXB => CASDOMUXB,             -- 1-bit input: Port B unregistered data (0=BRAM data, 1=CASDINB)
   CASDOMUXEN_A => CASDOMUXEN_A,       -- 1-bit input: Port A unregistered output data enable
   CASDOMUXEN_B => CASDOMUXEN_B,       -- 1-bit input: Port B unregistered output data enable
   CASOREGIMUXA => CASOREGIMUXA,       -- 1-bit input: Port A registered data (0=BRAM data, 1=CASDINA)
   CASOREGIMUXB => CASOREGIMUXB,       -- 1-bit input: Port B registered data (0=BRAM data, 1=CASDINB)
   CASOREGIMUXEN_A => CASOREGIMUXEN_A, -- 1-bit input: Port A registered output data enable
   CASOREGIMUXEN_B => CASOREGIMUXEN_B, -- 1-bit input: Port B registered output data enable
   -- Port A Address/Control Signals inputs: Port A address and control signals
   ADDRARDADDR => ADDRARDADDR,         -- 11-bit input: A/Read port address
   ARST_A => ARST_A,                   -- 1-bit input: Port A asynchronous reset
   CLKARDCLK => CLKARDCLK,             -- 1-bit input: A/Read port clock
   ENARDEN => ENARDEN,                 -- 1-bit input: Port A enable/Read enable
   REGCEAREGCE => REGCEAREGCE,         -- 1-bit input: Port A register enable/Register enable
   RSTRAMARSTRAM => RSTRAMARSTRAM,     -- 1-bit input: Port A set/reset
   RSTREGARSTREG => RSTREGARSTREG,     -- 1-bit input: Port A register set/reset
   WEA => WEA,                         -- 2-bit input: Port A write enable
   -- Port A Data inputs: Port A data
   DINADIN => DINADIN,                 -- 16-bit input: Port A data/LSB data
   DINPADINP => DINPADINP,             -- 2-bit input: Port A parity/LSB parity
   -- Port B Address/Control Signals inputs: Port B address and control signals
   ADDRBWRADDR => ADDRBWRADDR,         -- 11-bit input: B/Write port address
   ARST_B => ARST_B,                   -- 1-bit input: Port B asynchronous reset
   CLKBWRCLK => CLKBWRCLK,             -- 1-bit input: B/Write port clock
   ENBWREN => ENBWREN,                 -- 1-bit input: Port B enable/Write enable
   REGCEB => REGCEB,                   -- 1-bit input: Port B register enable
   RSTRAMB => RSTRAMB,                 -- 1-bit input: Port B set/reset
   RSTREGB => RSTREGB,                 -- 1-bit input: Port B register set/reset
   SLEEP => SLEEP,                     -- 1-bit input: Sleep Mode
   WEBWE => WEBWE,                     -- 4-bit input: Port B write enable/Write enable
   -- Port B Data inputs: Port B data
   DINBDIN => DINBDIN,                 -- 16-bit input: Port B data/MSB data
   DINPBDINP => DINPBDINP              -- 2-bit input: Port B parity/MSB parity
);

-- End of RAMB18E5_inst instantiation

Verilog Instantiation Template


// RAMB18E5: 18K-bit Configurable Synchronous Block RAM
//           Versal AI Core series
// Xilinx HDL Language Template, version 2021.2

RAMB18E5 #(
   // CASCADE_ORDER_A, CASCADE_ORDER_B: "FIRST", "MIDDLE", "LAST", "NONE"
   .CASCADE_ORDER_A("NONE"),
   .CASCADE_ORDER_B("NONE"),
   // CLOCK_DOMAINS: "COMMON", "INDEPENDENT"
   .CLOCK_DOMAINS("INDEPENDENT"),
   // Collision check: "ALL", "GENERATE_X_ONLY", "NONE", "WARNING_ONLY"
   .SIM_COLLISION_CHECK("ALL"),
   // DOA_REG, DOB_REG: Optional output register (0, 1)
   .DOA_REG(1),
   .DOB_REG(1),
   // INITP_00 to INITP_07: Initial contents of parity memory array
   .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
   // INIT_00 to INIT_3F: Initial contents of data memory array
   .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
   .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
   // Initialization File: RAM initialization file
   .INIT_FILE("NONE"),
   // PartialReconfig: Skip initialization after partial reconfiguration
   .PR_SAVE_DATA("FALSE"),
   // Programmable Inversion Attributes: Specifies the use of the built-in programmable inversion
   .IS_ARST_A_INVERTED(1'b0),
   .IS_ARST_B_INVERTED(1'b0),
   .IS_CLKARDCLK_INVERTED(1'b0),
   .IS_CLKBWRCLK_INVERTED(1'b0),
   .IS_ENARDEN_INVERTED(1'b0),
   .IS_ENBWREN_INVERTED(1'b0),
   .IS_RSTRAMARSTRAM_INVERTED(1'b0),
   .IS_RSTRAMB_INVERTED(1'b0),
   .IS_RSTREGARSTREG_INVERTED(1'b0),
   .IS_RSTREGB_INVERTED(1'b0),
   // READ_WIDTH_A/B, WRITE_WIDTH_A/B: Read/write width per port
   .READ_WIDTH_A(0),                                                                 // 0-9
   .READ_WIDTH_B(0),                                                                 // 0-9
   .WRITE_WIDTH_A(0),                                                                // 0-9
   .WRITE_WIDTH_B(0),                                                                // 0-9
   // RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG", "REGCE")
   .RSTREG_PRIORITY_A("RSTREG"),
   .RSTREG_PRIORITY_B("RSTREG"),
   // RST_MODE_A, RST_MODE_B: Set synchronous or asynchronous reset.
   .RST_MODE_A("SYNC"),
   .RST_MODE_B("SYNC"),
   // SRVAL_A, SRVAL_B: Set/reset value for output
   .SRVAL_A(18'h00000),
   .SRVAL_B(18'h00000),
   // Sleep Async: Sleep function asynchronous or synchronous ("TRUE", "FALSE")
   .SLEEP_ASYNC("FALSE"),
   // WriteMode: "WRITE_FIRST", "NO_CHANGE", "READ_FIRST"
   .WRITE_MODE_A("NO_CHANGE"),
   .WRITE_MODE_B("NO_CHANGE")
)
RAMB18E5_inst (
   // Cascade Signals outputs: Multi-BRAM cascade signals
   .CASDOUTA(CASDOUTA),               // 16-bit output: Port A cascade output data
   .CASDOUTB(CASDOUTB),               // 16-bit output: Port B cascade output data
   .CASDOUTPA(CASDOUTPA),             // 2-bit output: Port A cascade output parity data
   .CASDOUTPB(CASDOUTPB),             // 2-bit output: Port B cascade output parity data
   // Port A Data outputs: Port A data
   .DOUTADOUT(DOUTADOUT),             // 16-bit output: Port A data/LSB data
   .DOUTPADOUTP(DOUTPADOUTP),         // 2-bit output: Port A parity/LSB parity
   // Port B Data outputs: Port B data
   .DOUTBDOUT(DOUTBDOUT),             // 16-bit output: Port B data/MSB data
   .DOUTPBDOUTP(DOUTPBDOUTP),         // 2-bit output: Port B parity/MSB parity
   // Cascade Signals inputs: Multi-BRAM cascade signals
   .CASDINA(CASDINA),                 // 16-bit input: Port A cascade input data
   .CASDINB(CASDINB),                 // 16-bit input: Port B cascade input data
   .CASDINPA(CASDINPA),               // 2-bit input: Port A cascade input parity data
   .CASDINPB(CASDINPB),               // 2-bit input: Port B cascade input parity data
   .CASDOMUXA(CASDOMUXA),             // 1-bit input: Port A unregistered data (0=BRAM data, 1=CASDINA)
   .CASDOMUXB(CASDOMUXB),             // 1-bit input: Port B unregistered data (0=BRAM data, 1=CASDINB)
   .CASDOMUXEN_A(CASDOMUXEN_A),       // 1-bit input: Port A unregistered output data enable
   .CASDOMUXEN_B(CASDOMUXEN_B),       // 1-bit input: Port B unregistered output data enable
   .CASOREGIMUXA(CASOREGIMUXA),       // 1-bit input: Port A registered data (0=BRAM data, 1=CASDINA)
   .CASOREGIMUXB(CASOREGIMUXB),       // 1-bit input: Port B registered data (0=BRAM data, 1=CASDINB)
   .CASOREGIMUXEN_A(CASOREGIMUXEN_A), // 1-bit input: Port A registered output data enable
   .CASOREGIMUXEN_B(CASOREGIMUXEN_B), // 1-bit input: Port B registered output data enable
   // Port A Address/Control Signals inputs: Port A address and control signals
   .ADDRARDADDR(ADDRARDADDR),         // 11-bit input: A/Read port address
   .ARST_A(ARST_A),                   // 1-bit input: Port A asynchronous reset
   .CLKARDCLK(CLKARDCLK),             // 1-bit input: A/Read port clock
   .ENARDEN(ENARDEN),                 // 1-bit input: Port A enable/Read enable
   .REGCEAREGCE(REGCEAREGCE),         // 1-bit input: Port A register enable/Register enable
   .RSTRAMARSTRAM(RSTRAMARSTRAM),     // 1-bit input: Port A set/reset
   .RSTREGARSTREG(RSTREGARSTREG),     // 1-bit input: Port A register set/reset
   .WEA(WEA),                         // 2-bit input: Port A write enable
   // Port A Data inputs: Port A data
   .DINADIN(DINADIN),                 // 16-bit input: Port A data/LSB data
   .DINPADINP(DINPADINP),             // 2-bit input: Port A parity/LSB parity
   // Port B Address/Control Signals inputs: Port B address and control signals
   .ADDRBWRADDR(ADDRBWRADDR),         // 11-bit input: B/Write port address
   .ARST_B(ARST_B),                   // 1-bit input: Port B asynchronous reset
   .CLKBWRCLK(CLKBWRCLK),             // 1-bit input: B/Write port clock
   .ENBWREN(ENBWREN),                 // 1-bit input: Port B enable/Write enable
   .REGCEB(REGCEB),                   // 1-bit input: Port B register enable
   .RSTRAMB(RSTRAMB),                 // 1-bit input: Port B set/reset
   .RSTREGB(RSTREGB),                 // 1-bit input: Port B register set/reset
   .SLEEP(SLEEP),                     // 1-bit input: Sleep Mode
   .WEBWE(WEBWE),                     // 4-bit input: Port B write enable/Write enable
   // Port B Data inputs: Port B data
   .DINBDIN(DINBDIN),                 // 16-bit input: Port B data/MSB data
   .DINPBDINP(DINPBDINP)              // 2-bit input: Port B parity/MSB parity
);

// End of RAMB18E5_inst instantiation

Related Information

  • Versal ACAP Memory Resources Architecture Manual (AM007)