When you upgrade your Vivado tools to the latest release, Xilinx recommends that you upgrade the block design with the latest IP versions, make any necessary design changes, validate the design, and generate target output products.
You can also selectively upgrade only some of the IP inside the block design.
To use this feature, the block design must be fully generated in the previous release of
the Vivado tools. Xilinx highly recommends saving a backup copy of your project before
upgrading. When the IP upgrade status appears, uncheck any IP that do not need to be
upgraded. The LOCK_UPGRADE property is applied to the
IP that are not upgraded, and this property appears next to the IP in the Tcl Console
messages. The rest of the IP in the design are upgraded as in the normal flow.