Versal devices allow clock tile splitting among multiple RPs. After you specify the range for the clock sources (e.g., MMCM and BUFG) to the Pblock, the DFX flow automatically uses the required clocking tiles for routing.
The following figure shows the RCLK row and the vertical NoC (VNoC) column sharing multiple RPs. In the RCLK row, two RPs share the same clock region; one above the RCLK row and one below. The VNoC tiles are also shared between multiple RPs.
Recommended: If your design
includes more than two RPs, Xilinx recommends
keeping a clock region gap between the RPs so the RP internal clocks do not attempt to
use clock routing in the same VNoC tile. If more than two RPs attempt to use clock
routing in a single VNoC column, an unroutable situation might occur.
Figure 1. RCLK Row and Vertical NoC Column Sharing Multiple RPs
