Creating a Design with NoC IP - 2021.2 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)
Document ID
UG1387
Release Date
2021-11-19
Version
2021.2 English

In the Vivado IP integrator, the network on chip (NoC) IP acts as logical representation of the physical NoC. A Versal ACAP platform design might include multiple instances of each of the axi_noc and axis_noc IP cores. Each instance specifies one or more connections to be mapped onto the physical NoC, along with the Quality of Service (QoS) requirements for each connection.

The Vivado IP integrator automatically aggregates the connectivity and QoS information from all of the logical NoC instances to form a unified traffic specification. This traffic specification is used to compute an optimal configuration for the NoC. You can use the IP integrator to customize and generate NoC IP cores. The IP configuration allows you to set the number and type of input and output ports, define the connectivity through the NoC, and specify the memory controller configuration.

Note: For more information on the NoC and integrated memory controller IP, see the Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).
Power Tip: After the NoC design is complete, you can estimate power for the design using report_power in the Vivado Design Suite or using the Xilinx Power Estimator (XPE). To use the XPE, import the NOC_Power.xpe file from the NoC design into XPE to get a more accurate estimation of the NoC and total system power.