When larger portions of the clock network can be shut down for periods of time, you can enable or disable the clock network using a BUFGCE or BUFGCTRL.
When a clock can be slowed down during periods of time, you can also use these buffers with additional logic to periodically enable the clock net. Alternatively, you can use a BUFGMUX or BUFGCTRL to switch the clock source from a faster clock signal to a slower clock.
Any of these techniques can effectively reduce dynamic power. However, depending on the requirements and clock topology, one technique may prove more effective than another.
Important: When targeting Versal devices, do not gate a global
clock buffer in the MMCME5 feedback path (between the CLKFBOUT and CLKFBIN pins) using
the MMCME5 LOCKED signal. This will result in the MMCME5 failing to achieve lock.