The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 11/19/2021 Version 2021.2 | |
| Platform-Based Design Flow Best Practices | Added new section. |
| Design Planning Considerations for Dynamic Function eXchange | Added information on DFX Decoupler IP and added graphic. |
| Using Different Source Files in IP Integrator | Updated table. |
| Inter-NoC Interfaces | Added links to Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313). |
| NoC and QoS Requirements | Added link to Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313). |
| Creating a Hardware Platform for the Platform-Based Design Flow | Added graphics. |
| Clock Primitives | Added table for clock buffers. |
| Using the CLOCK_DEDICATED_ROUTE Constraint | Added graphic for CLOCK_DEDICATED_ROUTE constraint set to ANY_CMT_REGION. |
| Clock Phase Shift Modeling | Added new section. |
| PLL/MMCM Inverted Clocks | Added note about PHASESHIFT_MODE=LATENCY. |
| Boundary Clock Nets | Added example. |
| Reduce the Number of Partition Pins | Added PPLOC examples and graphics. |
| Make Pblocks as Rectangular as Possible to Avoid Unroutability at the Edges | Updated examples. |
| Avoid Disjointed Pblocks for Better Routability and Timing Closure | Added new section. |
| Specifying the RAM Activity for Jitter | Added details on pessimistic estimate performed by Vivado tool. |
| Incremental Synthesis | Added information on different modes. |
| Embedded Platform Creation for the Vitis Environment | Added note that process is iterative. |
| 07/26/2021 Version 2021.1 | |
| System Design Types | Revised traditional and platform-based design flows summary. |
| Design Planning | Added new chapter. |
| Design Creation with Block Designs | Updated introduction. |
| Methods for Using Block Designs with IP Integrator | Added new sections. |
| Creating a Design with CIPS IP | Added information on automation. |
| NoC IP DDR4 Memory Controllers | Added new section. |
| Creating a Hardware Platform for the Platform-Based Design Flow | Added new section. |
| Design Creation with RTL | Updated IP integrator requirement. |
| Auto-Pipelining Considerations | Added new section. |
| Coding for FIFOs | Added new section. |
| Coding Recommendations for Creating and Packaging RTL Kernels for the Platform-Based Design Flow | Added new section. |
| Clock Routing, Root, and Distribution | Added example and updated figure. |
| Clock Tree Placement and Routing | Clarified physical optimizer and clock network interaction. |
| Using the GCLK_DESKEW Property on a Clock Net | Added new section. |
| Gating the Clock Buffer | Added note about MMCME5 feedback path. |
| Clocking Recommendations for Platforms and Dynamic Function eXchange | Added new section. |
| Vitis HLS Methodology | Added new sections. |
| Design Constraints | Added note about traditional and platform-based design flows. |
| Constraining Input and Output Ports | Added note about I/O logic. |
| Defining Power and Thermal Constraints | Added new section. |
| Floorplanning Constraints for Dynamic Function eXchange | Added new section. |
| Specifying the RAM Activity for Jitter | Added new section. |
| Running Synthesis | Added note about IP integrator. |
| NoC Compiler Runs During Placement | Added new section. |
| Creating the Device Image | Added information on DRC and DFX considerations. |