The USER_RAM_AVERAGE_ACTIVITY constraint specifies a value that represents the average frequency of all UltraRAM and Block RAM on the device that can be switched (enabled/disabled). The value is used by the Vivado tools to model power supply noise induced by RAM switching and calculate jitter for global clocks in static timing analysis. The jitter is reported as a component of clock uncertainty in static timing analysis.
The Vivado tool performs a pessimistic estimate of RAM
activity for flat designs and assume a pessimistic value of 480 MHz for DFX designs. The
value computed by the Vivado tools is applied to the read-only
RAM_AVERAGE_ACTIVITY property on the top-level [current_design] object. If the USER_RAM_AVERAGE_ACTIVITY is not
specified, the pessimistic RAM_AVERAGE_ACTIVITY value computed by the Vivado tools is used for the jitter calculation and can increase the
difficulty of timing closure.
To specify the USER_RAM_AVERAGE_ACTIVITY constraint, apply the constraint to
the top-level [current_design] object in your XDC
constraints:
set_property USER_RAM_AVERAGE_ACTIVITY 160 [current_design]The following table shows how additional clock uncertainty caused by RAM switching can impact timing closure. In this example, a design has global clocks operating at 300 MHz, 400 MHz, and 500 MHz. The RAM_AVERAGE_ACTIVITY is 480, and the USER_RAM_AVERAGE_ACTIVITY constraint is calculated to be 160. Applying the constraint decreases the clock uncertainty for all paths in each clock domain, which makes achieving design timing closure less difficult.
| Clock Domain | RAM_AVERAGE_ACTIVITY 480 Clock Uncertainty | USER_RAM_AVERAGE_ACTIVITY 160 Clock Uncertainty | Clock Uncertainty Decrease |
|---|---|---|---|
| 300 MHz | 0.133 ns | 0.073 ns | -0.060 ns |
| 400 MHz | 0.122 ns | 0.066 ns | -0.056 ns |
| 500 MHz | 0.088 ns | 0.058 ns | -0.030 ns |