Using the GCLK_DESKEW Property on a Clock Net - 2021.2 English

You can use the GCLK_DESKEW property to disable calibrated deskew for a clock net. For some clocking topologies, it is more important to minimize insertion delay, and clock network deskew is less important for timing closure. In these cases, you can implement a clock network without additional delays to balance clock skew by setting the GCLK_DESKEW property on a clock net to OFF. This also disables calibrated deskew for the clock net. You must set the GCLK_DESKEW property on the net segment directly driven by the clock buffer. Following is an example:

set_property GCLK_DESKEW OFF [get_nets -of [get_pins clkgen/BUFG_clkout2_inst/O]]