Boundary logic interface flip-flops exist in hardware between the AI Engine-programmable logic (PL) interface, which you can use to improve timing. You can apply boundary logic interface (BLI) constraints to flip-flops in your design to automatically take advantage of this hardware feature during design placement. In this example, the AXI4-Stream interface for the AI Engine (AXI_PL_M_AXIS64) has connections to and from the fabric driven by flip-flops. Following is an example of the BLI constraints:
set_property BLI TRUE [get_cells m_axis_tdata_reg[*]]
set_property BLI TRUE [get_cells m_axis_*_reg]
The following figure shows the resulting placement and connectivity from setting the BLI property to TRUE.
For timing critical designs, enabling the BLI registers helps to achieve the highest performance. To control the inference of BLI registers across the AI Engine-PL channels, use the following AI Engine compiler options:
Specify clock frequency for PL kernels in MHz. The default value is 1/4 of AI Engine core frequency, which varies for each speed grade.
Following are examples:
- Same AI Engine-PL 300 MHz
frequency for all AI Engine-PL
- Different AI Engine-PL
frequency for different interfaces. Each interface is associated to a
different AI Engine graph PLIO. The
constraints must refer to the PLIO name, not the PL kernel
--pl-freq=plio_user_port_0:153 -pl-freq= plio_user_port_0:307.2
- Same AI Engine-PL 300 MHz frequency for all AI Engine-PL interfaces:
Specify frequency threshold for registered AI Engine-PL crossing in MHz. The default value is 1/8 of the AI Engine frequency based on speed grade.
Following is an example:
Any PLIO with an AI Engine-PL frequency higher than this setting (125 MHz in this case) is mapped to high-speed channels with the BLI registers enabled. If not, any AI Engine-PL channel can be used.