Tip: Given the flexibility of the Versal device clocking architecture, the
report_methodologycommand contains checks to aid you in creating an optimal clocking topology.
The following techniques cover the most common scenarios:
- Avoid timing paths between cascaded clock buffers by eliminating unnecessary buffers or connecting them in parallel as shown in the following figure.
Figure 1. Synchronous Clocking Topology with Cascaded BUFG Reconnected in Parallel
- Combine parallel clock buffers into a single clock buffer and
connect any clock buffer clock enable logic to the corresponding sequential cell
enable pins, as shown on figure below. If some of the clocks are divided by the
buffer's built-in divider, implement the equivalent division with clock enable logic
and apply multicycle path timing exceptions as needed. When both rising and falling
clock edges are used by the downstream logic or when power is an important factor,
this technique might not be applicable.Figure 2. Synchronous Clocking Topology with Parallel Clock Buffer Recombined into a Single Buffer
- Remove LUTs or any combinatorial logic in clock paths as they make
clock delays and clock skew unpredictable during placement, resulting in lower
quality of results. Also, a portion of the clock path is routed with general
interconnect resources which are more sensitive to noise than global clocking
resources. Combinatorial logic usually comes from sub-optimal clock gating
conversion and can usually be moved to clock enable logic, either connected to the
clock buffer or to the sequential cells.
In the following figure, the first BUFG (
clk1_buf) is used in LUT3 to create a gated clock condition.Figure 3. Skew Due to Local Routing on Clock Network