The following procedure helps track your progress towards timing closure and identify potential bottlenecks:
- Open the synthesized design.
report_timing_summary -delay_type min_max, and record the information shown in the following table.
Table 1. Timing Summary Report for Synthesized Design WNS TNS Num Failing Endpoints WHS THS Num Failing Endpoints Synth
- Open the post-synthesis
report_timing_summarytext report and record the
Number of missing clock requirements in the design: ___________
report_clock_networksto identify primary clock source pins/ports in the design.
Number of unconstrained clocks in the design: ___________
report_clock_interaction -delay_type min_maxand sort the results by WNS path requirement.
Smallest WNS path requirement in the design: ___________
- Sort the results of
report_clock_interactionby WHS to see if there are large hold violations (>500 ps) after synthesis.
Largest negative WHS in the design: ___________
- Sort results of
report_clock_interactionby Inter-Clock Constraints and list all the clock pairs that show up as unsafe.
- Upon opening the synthesized design, how many Critical Warnings
Number of synthesized design Critical Warnings: ___________
- What types of Critical Warnings exist?
Record examples of each type.
report_high_fanout_nets -timing -load_types -max_nets 25.
Number of high fanout nets not driven by FF: ___________
Number of loads on highest fanout net not driven by FF: ___________
Do any high fanout nets have negative slack? If yes, WNS = ___________
- Implement the design. After each step, run
report_timing_summaryand record the information shown in the following table.
Table 2. Timing Summary Report WNS TNS Num Failing Endpoints WHS THS Num Failing Endpoints Opt Place Physopt Route
report_exceptions -ignoredto identify if there are constraints that overlap in the design. Record the results.