Debugging AXI Interfaces in Vivado Hardware Manager - 2021.2 English

Versal ACAP System Integration and Validation Methodology Guide (UG1388)

Document ID
UG1388
Release Date
2021-11-19
Version
2021.2 English

The AXIS-ILA allows you to perform in-system debugging of post-implemented designs on a Xilinx device. Use this feature when there is a need to monitor interfaces and signals in the design.

If you changed the AXIS-ILA mode to Interface, you can debug and monitor AXI transactions and read and write events in the Waveform window shown in the following figure. The Waveform window displays the interface slots, transactions, events, and signal groups that correspond to the interfaces probed by the interface slots on the AXIS-ILA.

Figure 1. Waveform Window

For more information on AXIS-ILA and debugging AXI interfaces in the Vivado Hardware Manager, see this link and this link in the Vivado Design Suite User Guide: Programming and Debugging (UG908).