Confirm if the PS/PMC PLLs are stable and locked, clocks are in active state, and their divisor, multiplier, and source are correctly configured.
- Check the clocks configured correctly to each module with respect to speed grade.
- Read the CRx (CRL, CRF and CRP) modules registers for checking clocking.
To read the QSPI Clock Register using XSCT, run the following command:
xsct%mrd -force 0xF1260118
|Register Name||Address||Width||Type||Reset Value||Description|
|QSPI_REF_CTRL||0xF1260118||32||RW||0x01000400||This register controls this reference clock|
|Field Name||Bits||Type||Reset Value||Description|
|ClkAct||24||RW||0x1||Clock active signal.
0 = disable the clock.
1 = enable the clock.
|Divisor||17:8||RW||0x4||10-bit divider value:
0 = divide by 1
1 = divide by 1
2 = divide by 2
1023 = divide by 1023
Note: Reset value (0x4) is divided by 4.