The Vivado tools provide several methods to add debug probes in your design. The table below explains the various methods, including the pros and cons of each method.
|Debugging Flow Name
|HDL instantiation probing flow
|Explicitly attach signals in the HDL source or IP-Integrator canvas to an ILA debug core instance.
|Netlist insertion probing flow
Use one of the following two methods to identify the signal for debug:
Once the signal is marked for debug, use the Set up Debug wizard to guide you through the Netlist Insertion probing flow.
|Tcl-based netlist insertion probing flow