Reduce the Number of Control Sets - 2021.2 English

Versal ACAP System Integration and Validation Methodology Guide (UG1388)

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2021.2 English

If the number of control sets is high, use one of the following strategies to reduce their number:

  • Remove the MAX_FANOUT attributes that are set on control signals in the HDL sources or constraint files. Replication on control signals dramatically increases the number of unique control sets. Xilinx recommends relying on place_design to perform coarse replication and using phys_opt_design -directive Explore for finer replication after placer. This prevents unnecessary replication and equivalent control sets from crossing each other, which can lead to routing congestion.
  • Increase the control set threshold of Vivado synthesis (or other synthesis tool). Review the control sets fanout distribution table in report_control_sets -verbose to determine a more appropriate control sets threshold to use during synthesis. Note that increasing contol_set_opt can have negative impacts on power by eliminating clock enables that can actively reduce power. For example:
    synth_design -control_set_opt_threshold 16 
    Tip: Use the BLOCK_SYNTH synthesis constraints to change the control sets threshold on modules that are the most impacted by placement spreading or congestion.
  • Use opt_design -control_set_merge or opt_design -merge_equivalent_drivers to merge equivalent control sets after synthesis.
  • Use the CONTROL_SET_REMAP property to map low-fanout control signals driving the synchronous set/reset and/or CE pin of a register to the D-input. For more information, see this link in the Vivado Design Suite User Guide: Implementation (UG904).
  • Avoid low fanout asynchronous set/reset (preset/clear), because they can only be connected to dedicated asynchronous pins and cannot be moved to the datapath by synthesis. For this reason, the synthesis control set threshold option does not apply to asynchronous set/reset.
  • Avoid using both active-High and active-Low of a control signal for different sequential cells.
  • Only use clock enable and set/reset when necessary. Often data paths contain many registers that automatically flush uninitialized values, and where set/reset or enable signals are only needed on the first and last stages.
Note: For additional synthesis attributes and recommendations on control signals, see this link in the Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387).