Revision History - 2021.2 English

Versal ACAP System Integration and Validation Methodology Guide (UG1388)

Document ID
Release Date
2021.2 English

The following table shows the revision history for this document.

Section Revision Summary
11/19/2021 Version 2021.2
NoC Emulation Added NoC DDRMC AXI Traffic Generator GitHub link.
Design Closure Added QoS note.
ML Strategies Added non-project mode description and ML strategy suggestions.
System Performance Closure Added QoS note.
Debug Steps Updated increase latency description in Switches/IOMMU/Processor Links section and added PCIe debug note.
Improving Performance Through the NoC Added ChipScoPy description.
Improving Performance in the AI Engine Added hardware execution for AI engine. Added GitHub link and updated UG1416 links.
Debugging Added ChipScoPy description.
JTAG Status and Error Status Added FEC and LEC to Bits[147:136, 135:124].
Debugging the NoC and DDRMC Updated title and updated AM019, ACAP Cockpit, and PG313 links.
Connecting a Net to a Free External Pin Using Post-Route ECO Updated section.
07/26/2021 Version 2021.1
Logic Simulation Using SystemC Models Added CIPS VIP to table.
NoC Emulation Added PG313 link and updated title.
Design Closure Updated design closure description.
Timing Closure Added timing result note and added report_qor_suggestions note throughout subsections.
Checking for Valid Constraints Added baselining design to note.
Checking for Positive Timing Slacks Updated to timing score description.
Checking That Your Design is Properly Constrained Added timing constraint note.
Fixing Issues Flagged by report_methodology Added methodology violation note and link to methodology blog.
Methodology DRCs with Impact on Timing Closure Added UG906 link.
Assessing the Maximum Frequency of the Design Updated WNS description.
Analyzing and Resolving Timing Violations Updated Analyzing and Resolving Timing Violations figure.
Clock Skew and Uncertainty Added clock uncertainty description and related links.
Reducing Clock Delay in Versal Devices Added section.
Power Closure Added power optimization capabilities description.
Power Timing Slack Added section.
Analyzing System Performance for Platform-Based Designs Updated title and added traditional design note.
Analyzing AI Engine Performance in Simulation Added AI Engine bottleneck description.
Measuring Performance with AI Engine Run Time Event APIs Updated event API code block.
JTAG Status and Error Status Added POR description.
Rails Voltage Status Updated Register PWR_SUPPLY_STATUS Bit-Field Details table.
Debugging the NoC and DDRMC Added section.
Debugging with SmartLynq+ Added SmartLynq+ link.
Using VIO Cores Added link to PG364.
Using IBERT GTY for Transceiver Link Characterization Added link to PG331.
Using the ChipScoPy Python Client for Debugging Added section.
Debugging the Software Added section.
Performance Validation Added link to UG1076.