Using MBUFGCE to Reduce Clock Uncertainty - 2021.2 English

Versal ACAP System Integration and Validation Methodology Guide (UG1388)

Document ID
UG1388
Release Date
2021-11-19
Version
2021.2 English
Note: This optimization technique is automatically applied by the report_qor_suggestions Tcl command.
In Versal devices, you can use MBUFGCE cells to reduce clock uncertainty on synchronous clock domain crossings by eliminating MMCM phase error. For example, consider a path between a 300 MHz and 150 MHz clock domains, where both clocks are generated by the same MMCM.
Note: The parallel BUFGCE_DIV topology recommended for UltraScaleā„¢ devices can be used in Versal devices. However, the parallel BUFGCE_DIV topology uses more power, uses more clocking resources, and incurs more skew versus using the leaf-level division of the MBUFGCE.

In this case, the clock uncertainty includes 120 ps of phase error for both setup and hold analysis. Instead of generating the 150 MHz clock with the MMCM, an MBUFGCE can be connected to the 300 MHz MMCM output and divide the clock by 2 at the leaf-level.

Figure 1. Improving the Clock Topology for a Versal ACAP Synchronous CDC Timing Path

Following are improvements with the new topology:

  • For setup analysis, clock uncertainty does not include the MMCM phase error and is reduced by 120 ps.
  • For hold analysis, there is no more clock uncertainty (only for same-edge hold analysis).
  • The common node moves close to the leaf-level dividers, which reduces some clock pessimism.

The following tables compare the clock uncertainty for setup and hold analysis of a Versal ACAP synchronous CDC timing path.

Table 1. Comparison of Clock Uncertainty for Setup Analysis of a Versal ACAP Synchronous CDC Timing Path
Setup Analysis MMCM Generated 150 MHz Clock MBUFGCE 150 MHz Clock
  Clock Jitter (CJ) 0.405 ns 0.403 ns
Phase Jitter (PJ) 0.000 ns 0.000 ns
Phase Error (PE) 0.120 ns 0.000 ns
Clock Uncertainty 0.322 ns 0.202 ns
Table 2. Comparison of Clock Uncertainty for Hold Analysis of a Versal ACAP Synchronous CDC Timing Path
Hold Analysis MMCM Generated 150 MHz Clock MBUFGCE 150 MHz Clock
  Clock Jitter (CJ) 0.402 ns 0.000 ns
Phase Jitter (PJ) 0.000 ns 0.000 ns
Phase Error (PE) 0.120 ns 0.000 ns
Clock Uncertainty 0.322 ns 0.000 ns