When the C/RTL co-simulation completes, the simulation report opens and shows the measured latency and II. These results may differ from values reported after HLS synthesis, which are based on the absolute shortest and longest paths through the design. The results provided after C/RTL co-simulation show the actual values of latency and II for the given simulation data set (and may change if different input stimuli is used).
In non-pipelined designs, C/RTL co-simulation measures latency between
signals. The II is 1 more than the latency, because the design reads new inputs 1 cycle
after all operations are complete. The design only starts the next transaction after the
current transaction is complete.
In pipelined designs, the design might read new inputs before the first
transaction completes, and there might be multiple
ap_ready signals before a
transaction completes. In this case, C/RTL co-simulation measures the latency as the
number of cycles between data input values and data output values. The II is the number
of cycles between
ap_ready signals, which the design
uses to requests new inputs.